DCORE_OFFSET
u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET;
u32 edma_offset = dcore * DCORE_OFFSET + edma_idx * DCORE_EDMA_OFFSET;
cq_lbw_l_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 + DCORE_OFFSET;
cq_lbw_h_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 + DCORE_OFFSET;
cq_lbw_data_addr = mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 + DCORE_OFFSET;
cq_base_l_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 + DCORE_OFFSET;
cq_base_h_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 + DCORE_OFFSET;
cq_size_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 + DCORE_OFFSET;
cq_lbw_l_addr += DCORE_OFFSET;
cq_lbw_h_addr += DCORE_OFFSET;
cq_lbw_data_addr += DCORE_OFFSET;
cq_base_l_addr += DCORE_OFFSET;
cq_base_h_addr += DCORE_OFFSET;
cq_size_addr += DCORE_OFFSET;
mon_sts_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0 + DCORE_OFFSET;
mon_cfg_addr = mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + DCORE_OFFSET;
mon_sts_addr += DCORE_OFFSET;
mon_cfg_addr += DCORE_OFFSET;
addr = mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + DCORE_OFFSET;
addr += DCORE_OFFSET;
base = mmDCORE0_DEC0_CMD_BASE + dcore_id * DCORE_OFFSET +
offset = (DCORE_OFFSET * dcore) + (DCORE_TPC_OFFSET * inst);
mmDCORE0_SYNC_MNGR_OBJS_BASE + i * DCORE_OFFSET;
mmDCORE0_SYNC_MNGR_GLBL_BASE + i * DCORE_OFFSET;
qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET +
core_base = mmDCORE0_EDMA0_CORE_BASE + dcore * DCORE_OFFSET +
qm_base = mmDCORE0_EDMA0_QM_BASE + dcore * DCORE_OFFSET +
offset = dcore_id * DCORE_OFFSET + dec_id * DCORE_VDEC_OFFSET;
dcore_id * DCORE_OFFSET +
offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);
offset = (u32) (dcore_id * DCORE_OFFSET + hmmu_id * DCORE_HMMU_OFFSET);
offset = i * DCORE_OFFSET + j * DCORE_EDMA_OFFSET;
offset = i * DCORE_OFFSET;
offset = i * DCORE_OFFSET + j * DCORE_DEC_OFFSET;
dcore_vdec_id + DCORE_OFFSET * dcore_id;
u32 dcore_offset = dcore_id * DCORE_OFFSET;
dcore_id * DCORE_OFFSET +
(index / NUM_OF_TPC_PER_DCORE) * DCORE_OFFSET +
qman_base = mmDCORE0_MME_QM_BASE + index * DCORE_OFFSET;
DCORE_OFFSET * (dec_index / NUM_OF_DEC_PER_DCORE) +
sts_addr = mmDCORE0_MME_CTRL_LO_INTR_CAUSE + DCORE_OFFSET * mme_index;
sts_clr_addr = mmDCORE0_MME_CTRL_LO_INTR_CLEAR + DCORE_OFFSET * mme_index;
sts_addr = mmDCORE0_MME_ACC_INTR_CAUSE + DCORE_OFFSET * mme_index;
sts_clr_addr = mmDCORE0_MME_ACC_INTR_CLEAR + DCORE_OFFSET * mme_index;
sei_cause_addr = mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE + DCORE_OFFSET * sm_index;
cq_intr_addr = mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR + DCORE_OFFSET * sm_index;
return mmDCORE0_HMMU0_MMU_BASE + dcore * DCORE_OFFSET + index_in_dcore * DCORE_HMMU_OFFSET;
sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);
block_ctx.block_off = DCORE_OFFSET;
block_ctx.block_off = DCORE_OFFSET;
hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +
rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,