drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

50

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

46

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

45

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

49

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

750

DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

765

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

770

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

774

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

778

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

782

DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

46

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

866

DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

881

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

886

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

890

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

894

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

898

DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

62

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

676

DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

691

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

696

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

700

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

704

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

708

DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

70

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

63

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

42

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1492

DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1509

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1514

DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1518

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1522

DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1524

DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1528

DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1532

DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

649

DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

651

DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

657

DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

661

DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

666

DC_LOG_SMU("reg_name,value,clk_type");

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

668

DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

671

DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

674

DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

677

DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

680

DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

683

DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

686

DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

689

DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

692

DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

695

DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

698

DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass",

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

62

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

22

#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

616

DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n", support,