drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4375

int_params.irq_source < DC_IRQ_SOURCE_HPD1RX ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

532

for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

407

return (enum dc_irq_source)(DC_IRQ_SOURCE_HPD1RX +

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

105

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

385

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

100

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c

320

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

111

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

197

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

112

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

202

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

149

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

70

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

113

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

224

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

121

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

231

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

108

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

220

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

144

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

67

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

110

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

219

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

112

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

221

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

117

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

226

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

111

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

230

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

109

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

216

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

219

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

220

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

195

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

199

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

88

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

194

IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

197

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

87

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

210

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

91

return DC_IRQ_SOURCE_HPD1RX;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

635

link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

655

link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

664

link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

675

link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src;