Symbol: DCCG_SF
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
74
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
75
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
76
DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
77
DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
78
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
79
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
80
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
81
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
82
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
83
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
84
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
85
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
90
DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
45
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
46
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
47
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
48
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
49
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
50
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
51
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h
52
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
54
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
55
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
56
DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h
57
DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
47
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
48
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
49
DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
50
DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
51
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
52
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
53
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
54
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
55
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
56
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
57
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h
58
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
100
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
101
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
102
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
103
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
104
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
105
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
106
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
107
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
108
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
109
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
110
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
111
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
112
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
113
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
114
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
115
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
136
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
137
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
138
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
139
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
140
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
141
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
142
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
143
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
144
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
145
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
146
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
147
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
148
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
149
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
150
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
151
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
152
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
153
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
154
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
155
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
156
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
157
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
158
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
159
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
160
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
161
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
162
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
84
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
85
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
86
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
87
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
88
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
89
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
90
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
91
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
92
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
93
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
94
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
95
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
96
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
97
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
98
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
99
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
100
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
101
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
102
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
103
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
104
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
105
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
106
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
107
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
108
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
109
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
110
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
111
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
112
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
129
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
130
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
131
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
132
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
133
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
134
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
135
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
136
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
137
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
138
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
139
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
140
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
141
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
142
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
143
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
144
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
145
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
146
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
147
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
148
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
149
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
150
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
151
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
152
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
153
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
154
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
155
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
156
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
157
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
158
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
159
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
160
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
161
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
162
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
163
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
164
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
165
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
166
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
167
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
168
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
169
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
170
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
178
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
179
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
180
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
181
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
182
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
183
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
184
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
185
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
186
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
187
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
188
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
189
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
190
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
191
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
192
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_DTO_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
193
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
194
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
195
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
196
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
197
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
198
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
199
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
200
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
87
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
88
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
89
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
90
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
91
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
92
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
93
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
94
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
95
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
96
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
97
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
98
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
99
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
100
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
101
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
102
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
103
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
104
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
105
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
106
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
107
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
108
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
109
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
110
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
111
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
112
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
113
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
114
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
115
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
116
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
117
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh)
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
43
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
44
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
45
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
46
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
47
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
48
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
49
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
50
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
51
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
52
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
53
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
54
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
55
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
56
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
57
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
58
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
59
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
60
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
61
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
62
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
63
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
64
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
65
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
66
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
67
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
68
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
69
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
70
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
71
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
72
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
73
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
74
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
75
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
76
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
77
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
78
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
79
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
96
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
97
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
98
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h
99
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
100
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
101
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
102
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
119
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
120
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
121
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
122
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
123
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
124
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
125
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
126
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
127
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
132
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
133
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
134
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
135
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
136
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
137
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
138
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
139
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
140
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
141
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
142
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
143
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
144
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
145
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
146
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
147
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
148
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
149
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
150
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
151
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
152
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
153
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
154
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
155
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
156
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
157
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
158
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
159
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
160
DCCG_SF(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
161
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
162
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
163
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
164
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
165
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
166
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
167
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
168
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
169
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
170
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
171
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
172
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
173
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
174
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
175
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
176
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
177
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
178
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
179
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
180
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
181
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
182
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
183
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
184
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
185
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
186
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
187
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
188
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
189
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
190
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
191
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
192
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
193
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
194
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
195
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
196
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
197
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
198
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
199
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
200
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
201
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
202
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
203
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
204
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
205
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
206
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
207
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
208
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
209
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
210
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
211
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
212
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
213
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
214
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
215
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
216
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
217
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
218
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
219
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
220
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
221
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
222
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
223
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
224
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
225
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
226
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
227
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
228
DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
229
DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
230
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
231
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
232
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
233
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
234
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
235
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
236
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
237
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
238
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
239
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
240
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
241
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
242
DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
53
DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
54
DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
55
DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
56
DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
57
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
58
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
59
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
60
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
61
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
62
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
63
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
64
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
65
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
66
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
67
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
68
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
69
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
70
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
71
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
72
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
73
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
74
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
75
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
76
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
77
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
78
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
79
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
80
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
81
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
82
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
83
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
84
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
85
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
86
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
87
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
88
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
89
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
90
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
91
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
92
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
93
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
94
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
95
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
96
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
97
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
98
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
99
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
100
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
101
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
102
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
103
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
104
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
105
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
106
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
107
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
116
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
117
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
118
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
119
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
120
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
121
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
122
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
123
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
124
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
125
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
126
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
127
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
128
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
129
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
130
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
131
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
132
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
133
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
134
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
135
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
136
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
137
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
138
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
139
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
140
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
141
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
142
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
143
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
144
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
145
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
146
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
147
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
148
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
149
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
150
DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
151
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
152
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
153
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
154
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
155
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
156
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
157
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
158
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
159
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
160
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
161
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
162
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
163
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
164
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
165
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
166
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
167
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
168
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
169
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
170
DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
171
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
172
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
173
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
174
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
175
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
176
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
177
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
178
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
179
DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
180
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
181
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
182
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
183
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
184
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
185
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
186
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
187
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
188
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
189
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
190
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
191
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
39
DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
40
DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
41
DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
42
DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
43
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
44
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
45
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
46
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
47
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
48
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
49
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
50
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
51
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
52
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
53
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
54
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
55
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
56
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
57
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
58
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
59
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
60
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
61
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
62
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
63
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
64
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
65
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
66
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
67
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
68
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
69
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
70
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
71
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
72
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
73
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
74
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
75
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
76
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
85
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_TMDS_PIXEL_RATE_DIV, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
86
DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO0_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
87
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_TMDS_PIXEL_RATE_DIV, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
88
DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO1_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
89
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_TMDS_PIXEL_RATE_DIV, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
90
DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO2_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
91
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_TMDS_PIXEL_RATE_DIV, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
92
DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO3_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
93
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
94
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
95
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
96
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
97
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
98
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
99
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\