DCC
he_writel(he_dev, 0x0, DCC);
dcc += he_readl(he_dev, DCC);
AMD_FMT_MOD_GET(DCC, modifier)) {
if (AMD_FMT_MOD_GET(DCC, modifier))
AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) |
modifier |= AMD_FMT_MOD_SET(DCC, 1) |
return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
AMD_FMT_MOD_SET(DCC, 1) |
modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) |
uint64_t dcc = ver | AMD_FMT_MOD_SET(DCC, 1);
u32 dcc = intel_uncore_read(uncore, DCC);
intel_uncore_read(uncore, DCC));
PINGROUP(gpio_dis0_pu0, RSVD0, GP, DCB, DCC, 0x1080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
PINGROUP(gpio_dis3_pu3, RSVD0, RSVD1, DISPLAYB, DCC, 0x1098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
PINGROUP(gpio_dis5_pu5, RSVD0, GP, DCC, DCB, 0x10a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),