DBG1
DBG1("CTRL_UL");
DBG1("base_addr: %p", dc->base_addr);
DBG1("sending flow control 0x%04X", *((u16 *)&ctrl));
DBG1("SETTING DTR index: %d, dtr: %d", tty->index, dtr);
DBG1("open: %d", port->token_dl);
DBG1("close: %d", port->token_dl);
DBG1("ERR: 0x%08X, %d", cmd, cmd);
DBG1("Second phase, configuring card");
DBG1("toggle ports: MDM UL:%d MDM DL:%d, DIAG DL:%d",
DBG1("First phase: pushing upload buffers, clearing download");
DBG1("First phase done");
DBG1("No room in tty, don't read data, don't ack interrupt, "
DBG1("The Base Band sends this value as a response to a "
DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),
DBG1("Disable interrupt (0x%04X) on port: %d",
DBG1("Enable interrupt (0x%04X) on port: %d",
DBG1("Data in buffer [%d], enable transmit! ",
DBG1("No data in buffer...");
DBG1(" No change in mctrl");
DBG1("port: %d DCD(%d), CTS(%d), RI(%d), DSR(%d)",