DAR
OFFSET(DAR, thread_struct, dar);
stw r11, DAR(r10)
lwz r10, DAR(r12)
__raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR));
channel_readl(dwc, DAR),
channel_writel(dwc, DAR, lli_read(desc, dar));
DW_REG(DAR); /* Destination Address Register */
channel_writeq(idma64c, DAR, 0);
off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
sh_dmae_writel(sh_chan, hw->dar, DAR);
u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
channel64_readq(dc, DAR),
channel32_readl(dc, DAR),
channel_writeq(dc, DAR, 0);
channel_writel(dc, DAR, 0);
(u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
(u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
d->CHAR, d->SAR, d->DAR, d->CNTR);
d->CHAR, d->SAR, d->DAR, d->CNTR,
desc->hwdesc.DAR = dest + offset;
desc->hwdesc32.DAR = dest + offset;
desc->hwdesc.DAR = ds->tx_reg;
desc->hwdesc.DAR = mem;
desc->hwdesc32.DAR = ds->tx_reg;
desc->hwdesc32.DAR = mem;
u64 DAR;
u32 DAR;
u64 DAR; /* Destination Address Register */
u32 DAR;