zynq_qspi_write
zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,
zynq_qspi_write(xqspi, offset[size - 1], data);
zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);
zynq_qspi_write(xqspi,
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);