zl3073x_write_u8
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(index),
rc = zl3073x_write_u8(zldev,
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_DF_READ(index),
rc = zl3073x_write_u8(zldev, op_reg, op_val);
rc = zl3073x_write_u8(zldev, ZL_REG_HWREG_OP, op | ZL_HWREG_OP_PENDING);
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel);
rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0,
rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4,
rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL, type);
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask);
int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val);
rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f);
rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01);
rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01);
rc = zl3073x_write_u8(zldev, ZL_REG_WRITE_FLASH, value);
return zl3073x_write_u8(zldev, ZL_REG_HOST_CONTROL, host_ctrl);
rc = zl3073x_write_u8(zldev, ZL_REG_RESET_STATUS, reset_status);
rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, out->mode);
rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL,