xr_set_reg_um
ret = xr_set_reg_um(port, XR21V141X_UM_FIFO_ENABLE_REG,
ret = xr_set_reg_um(port, XR21V141X_UM_FIFO_ENABLE_REG,
ret = xr_set_reg_um(port, XR21V141X_UM_FIFO_ENABLE_REG, 0);
ret = xr_set_reg_um(port, XR21V141X_UM_TX_FIFO_RESET, XR_FIFO_RESET);
ret = xr_set_reg_um(port, XR21V141X_UM_RX_FIFO_RESET, XR_FIFO_RESET);