drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

139

#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

157

#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

158

#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

160

#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

161

#define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

162

#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

163

#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

164

#define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

165

#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

166

#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

205

#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

206

#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

207

#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

208

#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)

drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

58

#define RSIF_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 3)

drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

61

#define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)