xive_ops
rc = xive_ops->populate_irq_data(hw, xd);
if (xive_ops->get_ipi(cpu, xc))
rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
rc = xive_ops->configure_irq(xc->hw_ipi,
xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
xive_ops->put_ipi(cpu, xc);
return xive_ops->match(node);
xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
if (xive_ops->prepare_cpu)
xive_ops->prepare_cpu(cpu, xc);
if (xive_ops->setup_cpu)
xive_ops->setup_cpu(smp_processor_id(), xc);
if (xive_ops->teardown_cpu)
xive_ops->teardown_cpu(cpu, xc);
xive_ops->shutdown();
bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
xive_ops = ops;
xive_ops->name);
rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
if (xive_ops->debug_show)
xive_ops->debug_show(m, private);
if (xive_ops->debug_create)
xive_ops->debug_create(xive_dir);
if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
xive_ops->update_pending(xc);
static const struct xive_ops *xive_ops;
rc = xive_ops->configure_irq(hw_irq,
xive_ops->configure_irq(hw_irq,
rc = xive_ops->configure_irq(hw_irq,
if (xive_ops->sync_source)
xive_ops->sync_source(hw_irq);
if (xive_ops->sync_source)
xive_ops->sync_source(hw_irq);
rc = xive_ops->configure_irq(hw_irq,
static const struct xive_ops xive_native_ops = {
static const struct xive_ops xive_spapr_ops = {
bool xive_core_init(struct device_node *np, const struct xive_ops *ops,