drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

104

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

112

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

120

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

128

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

29

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

37

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

45

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

53

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

62

struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

63

struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

80

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

88

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

96

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/regs/xe_reg_defs.h

121

#define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))

drivers/gpu/drm/xe/regs/xe_reg_defs.h

133

static inline bool xe_reg_is_valid(struct xe_reg r)

drivers/gpu/drm/xe/regs/xe_reg_defs.h

62

static_assert(sizeof(struct xe_reg) == sizeof(u32));

drivers/gpu/drm/xe/regs/xe_reg_defs.h

73

struct xe_reg __reg;

drivers/gpu/drm/xe/tests/xe_rtp_test.c

51

struct xe_reg expected_reg;

drivers/gpu/drm/xe/tests/xe_rtp_test.c

66

static bool fake_xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)

drivers/gpu/drm/xe/xe_force_wake.c

32

struct xe_reg reg, struct xe_reg ack)

drivers/gpu/drm/xe/xe_force_wake_types.h

76

struct xe_reg reg_ctl;

drivers/gpu/drm/xe/xe_force_wake_types.h

78

struct xe_reg reg_ack;

drivers/gpu/drm/xe/xe_gt.c

289

struct xe_reg reg = entry->reg;

drivers/gpu/drm/xe/xe_gt_mcr.c

51

static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)

drivers/gpu/drm/xe/xe_gt_mcr.c

608

struct xe_reg reg,

drivers/gpu/drm/xe/xe_gt_mcr.c

629

bool xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg)

drivers/gpu/drm/xe/xe_gt_mcr.c

661

const struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.c

733

const struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.c

735

struct xe_reg steer_reg;

drivers/gpu/drm/xe/xe_gt_mcr.c

800

const struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.c

879

struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.h

29

bool xe_gt_mcr_check_reg(struct xe_gt *gt, struct xe_reg reg);

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

101

static const struct xe_reg ver_35_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

119

static const struct xe_reg *pick_runtime_regs(struct xe_device *xe, unsigned int *count)

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

121

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

155

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

183

const struct xe_reg *regs, u32 *values)

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

191

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

23

static const struct xe_reg tgl_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

33

static const struct xe_reg ats_m_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

410

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

44

static const struct xe_reg pvc_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

55

static const struct xe_reg ver_1270_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

68

static const struct xe_reg ver_2000_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

84

static const struct xe_reg ver_3000_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service_types.h

11

struct xe_reg;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service_types.h

32

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1087

u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg)

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1122

void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)

drivers/gpu/drm/xe/xe_gt_sriov_vf.h

13

struct xe_reg;

drivers/gpu/drm/xe/xe_gt_sriov_vf.h

35

u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg);

drivers/gpu/drm/xe/xe_gt_sriov_vf.h

36

void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);

drivers/gpu/drm/xe/xe_gt_throttle.c

87

struct xe_reg reg;

drivers/gpu/drm/xe/xe_gt_topology.c

21

const struct xe_reg regs[])

drivers/gpu/drm/xe/xe_gt_topology.c

211

static const struct xe_reg geometry_regs[] = {

drivers/gpu/drm/xe/xe_gt_topology.c

217

static const struct xe_reg compute_regs[] = {

drivers/gpu/drm/xe/xe_guc.c

1485

struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?

drivers/gpu/drm/xe/xe_guc_ads.c

706

struct xe_reg reg,

drivers/gpu/drm/xe/xe_guc_ads.c

742

struct xe_reg reg;

drivers/gpu/drm/xe/xe_guc_capture_types.h

31

struct xe_reg reg;

drivers/gpu/drm/xe/xe_guc_types.h

122

struct xe_reg notify_reg;

drivers/gpu/drm/xe/xe_huc.c

220

struct xe_reg reg;

drivers/gpu/drm/xe/xe_hw_engine.c

295

u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)

drivers/gpu/drm/xe/xe_hw_engine.h

79

u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);

drivers/gpu/drm/xe/xe_hwmon.c

1084

struct xe_reg reg;

drivers/gpu/drm/xe/xe_hwmon.c

1478

struct xe_reg pkg_power_sku_unit;

drivers/gpu/drm/xe/xe_hwmon.c

262

static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,

drivers/gpu/drm/xe/xe_hwmon.c

345

struct xe_reg rapl_limit, pkg_power_sku;

drivers/gpu/drm/xe/xe_hwmon.c

390

struct xe_reg rapl_limit;

drivers/gpu/drm/xe/xe_hwmon.c

475

struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);

drivers/gpu/drm/xe/xe_hwmon.c

708

struct xe_reg rapl_limit;

drivers/gpu/drm/xe/xe_hwmon.c

934

struct xe_reg vram_reg;

drivers/gpu/drm/xe/xe_irq.c

43

static void assert_iir_is_zero(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

144

u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

157

void xe_mmio_write8(struct xe_mmio *mmio, struct xe_reg reg, u8 val)

drivers/gpu/drm/xe/xe_mmio.c

166

u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

179

void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val)

drivers/gpu/drm/xe/xe_mmio.c

192

u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

210

u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set)

drivers/gpu/drm/xe/xe_mmio.c

222

struct xe_reg reg, u32 val, u32 mask, u32 eval)

drivers/gpu/drm/xe/xe_mmio.c

234

struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

263

u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

265

struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };

drivers/gpu/drm/xe/xe_mmio.c

291

static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,

drivers/gpu/drm/xe/xe_mmio.c

363

int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,

drivers/gpu/drm/xe/xe_mmio.c

382

int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,

drivers/gpu/drm/xe/xe_mmio.h

12

struct xe_reg;

drivers/gpu/drm/xe/xe_mmio.h

19

u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

20

void xe_mmio_write8(struct xe_mmio *mmio, struct xe_reg reg, u8 val);

drivers/gpu/drm/xe/xe_mmio.h

21

u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

22

void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);

drivers/gpu/drm/xe/xe_mmio.h

23

u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

24

u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);

drivers/gpu/drm/xe/xe_mmio.h

25

int xe_mmio_write32_and_verify(struct xe_mmio *mmio, struct xe_reg reg, u32 val, u32 mask, u32 eval);

drivers/gpu/drm/xe/xe_mmio.h

26

bool xe_mmio_in_range(const struct xe_mmio *mmio, const struct xe_mmio_range *range, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

28

u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

29

int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,

drivers/gpu/drm/xe/xe_mmio.h

31

int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,

drivers/gpu/drm/xe/xe_nvm.c

62

struct xe_reg reg;

drivers/gpu/drm/xe/xe_oa.c

2148

static const struct xe_reg flex_eu_regs[] = {

drivers/gpu/drm/xe/xe_oa.c

410

struct xe_reg oaheadptr = __oa_regs(stream)->oa_head_ptr;

drivers/gpu/drm/xe/xe_oa.c

67

struct xe_reg addr;

drivers/gpu/drm/xe/xe_oa_types.h

83

struct xe_reg oa_head_ptr;

drivers/gpu/drm/xe/xe_oa_types.h

84

struct xe_reg oa_tail_ptr;

drivers/gpu/drm/xe/xe_oa_types.h

85

struct xe_reg oa_buffer;

drivers/gpu/drm/xe/xe_oa_types.h

86

struct xe_reg oa_ctx_ctrl;

drivers/gpu/drm/xe/xe_oa_types.h

87

struct xe_reg oa_ctrl;

drivers/gpu/drm/xe/xe_oa_types.h

88

struct xe_reg oa_debug;

drivers/gpu/drm/xe/xe_oa_types.h

89

struct xe_reg oa_status;

drivers/gpu/drm/xe/xe_oa_types.h

90

struct xe_reg oa_mmio_trg;

drivers/gpu/drm/xe/xe_pat.c

335

struct xe_reg reg = XE_REG(_PAT_INDEX(i));

drivers/gpu/drm/xe/xe_pci.c

599

struct xe_reg gmdid_reg = GMD_ID;

drivers/gpu/drm/xe/xe_query.c

98

struct xe_reg upper_reg = RING_TIMESTAMP_UDW(hwe->mmio_base),

drivers/gpu/drm/xe/xe_reg_sr.c

111

struct xe_reg reg;

drivers/gpu/drm/xe/xe_reg_sr.c

161

static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg)

drivers/gpu/drm/xe/xe_reg_sr.c

168

struct xe_reg reg = entry->reg;

drivers/gpu/drm/xe/xe_reg_sr.c

251

static u32 readback_reg(struct xe_gt *gt, struct xe_reg reg)

drivers/gpu/drm/xe/xe_reg_sr.c

73

static struct xe_reg sanitize_mcr(struct xe_reg_sr *sr,

drivers/gpu/drm/xe/xe_reg_sr.c

77

struct xe_reg reg = e->reg;

drivers/gpu/drm/xe/xe_reg_sr_types.h

15

struct xe_reg reg;

drivers/gpu/drm/xe/xe_ring_ops.c

272

const struct xe_reg reg = xe_lrc_is_multi_queue(lrc) ?

drivers/gpu/drm/xe/xe_ring_ops.c

52

__emit_aux_table_inv(u32 *cmd, const struct xe_reg reg, u32 adj_offset)

drivers/gpu/drm/xe/xe_rtp_types.h

25

struct xe_reg reg;

drivers/gpu/drm/xe/xe_soc_remapper.c

11

static void xe_soc_remapper_set_region(struct xe_device *xe, struct xe_reg reg,

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

62

static const struct xe_reg regs[] = {

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

83

static const struct xe_reg regs[] = {