drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

114

xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

130

xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

90

xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);

drivers/gpu/drm/xe/xe_device.c

1158

xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0);

drivers/gpu/drm/xe/xe_device.c

1174

xe_mmio_write32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);

drivers/gpu/drm/xe/xe_device.c

1229

xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1);

drivers/gpu/drm/xe/xe_device.c

651

xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS);

drivers/gpu/drm/xe/xe_device.c

672

xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS);

drivers/gpu/drm/xe/xe_execlist.c

76

xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

80

xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

82

xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

84

xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base),

drivers/gpu/drm/xe/xe_force_wake.c

101

xe_mmio_write32(&gt->mmio, domain->reg_ctl, domain->mask | (wake ? domain->val : 0));

drivers/gpu/drm/xe/xe_ggtt.c

211

xe_mmio_write32(&affected_gt->mmio, GMD_ID, 0x0);

drivers/gpu/drm/xe/xe_gt.c

822

xe_mmio_write32(&gt->mmio, GDRST, GRDOM_FULL);

drivers/gpu/drm/xe/xe_gt_ccs_mode.c

79

xe_mmio_write32(&gt->mmio, CCS_MODE, mode);

drivers/gpu/drm/xe/xe_gt_idle.c

146

xe_mmio_write32(mmio, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25);

drivers/gpu/drm/xe/xe_gt_idle.c

147

xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);

drivers/gpu/drm/xe/xe_gt_idle.c

156

xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable);

drivers/gpu/drm/xe/xe_gt_idle.c

170

xe_mmio_write32(&gt->mmio, POWERGATE_ENABLE, gtidle->powergate_enable);

drivers/gpu/drm/xe/xe_gt_idle.c

412

xe_mmio_write32(&gt->mmio, RC_IDLE_HYSTERSIS, 0x3B9ACA);

drivers/gpu/drm/xe/xe_gt_idle.c

414

xe_mmio_write32(&gt->mmio, RC_CONTROL,

drivers/gpu/drm/xe/xe_gt_idle.c

429

xe_mmio_write32(&gt->mmio, RC_CONTROL, 0);

drivers/gpu/drm/xe/xe_gt_idle.c

430

xe_mmio_write32(&gt->mmio, RC_STATE, 0);

drivers/gpu/drm/xe/xe_gt_mcr.c

596

xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, steer_val);

drivers/gpu/drm/xe/xe_gt_mcr.c

597

xe_mmio_write32(&gt->mmio, SF_MCR_SELECTOR, steer_val);

drivers/gpu/drm/xe/xe_gt_mcr.c

720

xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, 0x1);

drivers/gpu/drm/xe/xe_gt_mcr.c

767

xe_mmio_write32(mmio, steer_reg, steer_val);

drivers/gpu/drm/xe/xe_gt_mcr.c

772

xe_mmio_write32(mmio, reg, value);

drivers/gpu/drm/xe/xe_gt_mcr.c

781

xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST);

drivers/gpu/drm/xe/xe_gt_mcr.c

889

xe_mmio_write32(&gt->mmio, reg, value);

drivers/gpu/drm/xe/xe_gt_sriov_pf.c

147

xe_mmio_write32(&gt->mmio, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN);

drivers/gpu/drm/xe/xe_gt_sriov_pf.c

173

xe_mmio_write32(&mmio, MED_VF_SW_FLAG(n), 0);

drivers/gpu/drm/xe/xe_gt_sriov_pf.c

176

xe_mmio_write32(&mmio, VF_SW_FLAG(n), 0);

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

410

xe_mmio_write32(&mmio, MED_VF_SW_FLAG(n), regs[n]);

drivers/gpu/drm/xe/xe_gt_sriov_pf_migration.c

413

xe_mmio_write32(&mmio, VF_SW_FLAG(n), regs[n]);

drivers/gpu/drm/xe/xe_guc.c

1019

xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags);

drivers/gpu/drm/xe/xe_guc.c

1021

xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE);

drivers/gpu/drm/xe/xe_guc.c

1040

xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);

drivers/gpu/drm/xe/xe_guc.c

1049

xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(i), rsa[i]);

drivers/gpu/drm/xe/xe_guc.c

1343

xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);

drivers/gpu/drm/xe/xe_guc.c

1361

xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(15), 0);

drivers/gpu/drm/xe/xe_guc.c

1378

xe_mmio_write32(&gt->mmio, GUC_SG_INTR_ENABLE,

drivers/gpu/drm/xe/xe_guc.c

1463

xe_mmio_write32(&gt->mmio, guc->notify_reg, default_notify_data);

drivers/gpu/drm/xe/xe_guc.c

1508

xe_mmio_write32(mmio, MED_VF_SW_FLAG(i),

drivers/gpu/drm/xe/xe_guc.c

1513

xe_mmio_write32(mmio, VF_SW_FLAG(i),

drivers/gpu/drm/xe/xe_guc.c

288

xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(0), 0);

drivers/gpu/drm/xe/xe_guc.c

291

xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(1 + i), guc->params[i]);

drivers/gpu/drm/xe/xe_guc.c

978

xe_mmio_write32(mmio, GDRST, GRDOM_GUC);

drivers/gpu/drm/xe/xe_guc_pc.c

326

xe_mmio_write32(&gt->mmio, RP_CONTROL, state);

drivers/gpu/drm/xe/xe_guc_pc.c

338

xe_mmio_write32(&gt->mmio, RPNSWREQ, rpnswreq);

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

88

xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

90

xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

93

xe_mmio_write32(mmio, GUC_TLB_INV_CR,

drivers/gpu/drm/xe/xe_hw_engine.c

307

xe_mmio_write32(&hwe->gt->mmio, RING_HWS_PGA(hwe->mmio_base),

drivers/gpu/drm/xe/xe_hw_engine.c

601

xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);

drivers/gpu/drm/xe/xe_hw_engine.c

833

xe_mmio_write32(&gt->mmio, GUNIT_GSC_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_hw_engine.c

834

xe_mmio_write32(&gt->mmio, GUNIT_GSC_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_hw_error.c

216

xe_mmio_write32(mmio, HEC_UNCORR_ERR_STATUS(base), err_src);

drivers/gpu/drm/xe/xe_hw_error.c

314

xe_mmio_write32(mmio, ERR_STAT_GT_REG(hw_err), err_stat);

drivers/gpu/drm/xe/xe_hw_error.c

337

xe_mmio_write32(mmio, ERR_STAT_GT_VECTOR_REG(hw_err, i), vector);

drivers/gpu/drm/xe/xe_hw_error.c

360

xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(slave, hw_err),

drivers/gpu/drm/xe/xe_hw_error.c

367

xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave, hw_err), slave_global_errstat);

drivers/gpu/drm/xe/xe_hw_error.c

388

xe_mmio_write32(mmio, SOC_GSYSEVTCTL_REG(master, slave, i), ~REG_BIT(hw_err));

drivers/gpu/drm/xe/xe_hw_error.c

391

xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err), REG_GENMASK(31, 0));

drivers/gpu/drm/xe/xe_hw_error.c

392

xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err), REG_GENMASK(31, 0));

drivers/gpu/drm/xe/xe_hw_error.c

393

xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave, hw_err), REG_GENMASK(31, 0));

drivers/gpu/drm/xe/xe_hw_error.c

394

xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(slave, hw_err), REG_GENMASK(31, 0));

drivers/gpu/drm/xe/xe_hw_error.c

413

xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err), master_local_errstat);

drivers/gpu/drm/xe/xe_hw_error.c

419

xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err), master_global_errstat);

drivers/gpu/drm/xe/xe_hw_error.c

423

xe_mmio_write32(mmio, SOC_GSYSEVTCTL_REG(master, slave, i),

drivers/gpu/drm/xe/xe_hw_error.c

491

xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), err_src);

drivers/gpu/drm/xe/xe_hw_error.c

539

xe_mmio_write32(&tile->mmio, GFX_MSTR_IRQ, master_ctl);

drivers/gpu/drm/xe/xe_i2c.c

270

xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val);

drivers/gpu/drm/xe/xe_irq.c

102

xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);

drivers/gpu/drm/xe/xe_irq.c

124

xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);

drivers/gpu/drm/xe/xe_irq.c

133

xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);

drivers/gpu/drm/xe/xe_irq.c

182

xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,

drivers/gpu/drm/xe/xe_irq.c

186

xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,

drivers/gpu/drm/xe/xe_irq.c

191

xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

193

xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

198

xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

200

xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

202

xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

204

xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

209

xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

211

xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

220

xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,

drivers/gpu/drm/xe/xe_irq.c

228

xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

230

xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

232

xe_mmio_write32(mmio, VCS4_VCS5_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

234

xe_mmio_write32(mmio, VCS6_VCS7_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

239

xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

241

xe_mmio_write32(mmio, VECS2_VECS3_INTR_MASK, val);

drivers/gpu/drm/xe/xe_irq.c

255

xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask);

drivers/gpu/drm/xe/xe_irq.c

256

xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~gsc_mask);

drivers/gpu/drm/xe/xe_irq.c

259

xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16));

drivers/gpu/drm/xe/xe_irq.c

266

xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_ENABLE, kcr_mask << 16);

drivers/gpu/drm/xe/xe_irq.c

267

xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_MASK, ~(kcr_mask << 16));

drivers/gpu/drm/xe/xe_irq.c

283

xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));

drivers/gpu/drm/xe/xe_irq.c

301

xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident);

drivers/gpu/drm/xe/xe_irq.c

373

xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);

drivers/gpu/drm/xe/xe_irq.c

449

xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);

drivers/gpu/drm/xe/xe_irq.c

456

xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);

drivers/gpu/drm/xe/xe_irq.c

465

xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);

drivers/gpu/drm/xe/xe_irq.c

514

xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);

drivers/gpu/drm/xe/xe_irq.c

53

xe_mmio_write32(mmio, reg, 0xffffffff);

drivers/gpu/drm/xe/xe_irq.c

55

xe_mmio_write32(mmio, reg, 0xffffffff);

drivers/gpu/drm/xe/xe_irq.c

555

xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

556

xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

558

xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

561

xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

562

xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

564

xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

566

xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

568

xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

570

xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

571

xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

572

xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

573

xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

575

xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

577

xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

582

xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

583

xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

584

xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

585

xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

586

xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

589

xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

590

xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

591

xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0);

drivers/gpu/drm/xe/xe_irq.c

592

xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0);

drivers/gpu/drm/xe/xe_irq.c

624

xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);

drivers/gpu/drm/xe/xe_irq.c

73

xe_mmio_write32(mmio, IER(irqregs), bits);

drivers/gpu/drm/xe/xe_irq.c

74

xe_mmio_write32(mmio, IMR(irqregs), ~bits);

drivers/gpu/drm/xe/xe_irq.c

85

xe_mmio_write32(mmio, IMR(irqregs), ~0);

drivers/gpu/drm/xe/xe_irq.c

89

xe_mmio_write32(mmio, IER(irqregs), 0);

drivers/gpu/drm/xe/xe_irq.c

92

xe_mmio_write32(mmio, IIR(irqregs), ~0);

drivers/gpu/drm/xe/xe_irq.c

94

xe_mmio_write32(mmio, IIR(irqregs), ~0);

drivers/gpu/drm/xe/xe_lmtt.c

229

xe_mmio_write32(&gt->mmio,

drivers/gpu/drm/xe/xe_lmtt.c

234

xe_mmio_write32(&tile->mmio, MERT_LMEM_CFG, config);

drivers/gpu/drm/xe/xe_mert.c

49

xe_mmio_write32(&tile->mmio, MERT_TLB_INV_DESC_A, MERT_TLB_INV_DESC_A_VALID);

drivers/gpu/drm/xe/xe_mert.c

67

xe_mmio_write32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT, 0);

drivers/gpu/drm/xe/xe_mmio.c

216

xe_mmio_write32(mmio, reg, reg_val);

drivers/gpu/drm/xe/xe_mmio.c

226

xe_mmio_write32(mmio, reg, val);

drivers/gpu/drm/xe/xe_mmio.h

22

void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);

drivers/gpu/drm/xe/xe_mocs.c

720

xe_mmio_write32(&gt->mmio, XELP_GLOBAL_MOCS(i), mocs);

drivers/gpu/drm/xe/xe_mocs.c

760

xe_mmio_write32(&gt->mmio, XELP_LNCFCMOCS(i), l3cc);

drivers/gpu/drm/xe/xe_oa.c

1131

xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,

drivers/gpu/drm/xe/xe_oa.c

1137

xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctx_ctrl,

drivers/gpu/drm/xe/xe_oa.c

2679

xe_mmio_write32(&gt->mmio, u->regs.oa_ctrl, 0);

drivers/gpu/drm/xe/xe_oa.c

2682

xe_mmio_write32(&gt->mmio, u->regs.oa_debug,

drivers/gpu/drm/xe/xe_oa.c

413

xe_mmio_write32(&stream->gt->mmio, oaheadptr,

drivers/gpu/drm/xe/xe_oa.c

439

xe_mmio_write32(mmio, __oa_regs(stream)->oa_status, 0);

drivers/gpu/drm/xe/xe_oa.c

440

xe_mmio_write32(mmio, __oa_regs(stream)->oa_head_ptr,

drivers/gpu/drm/xe/xe_oa.c

447

xe_mmio_write32(mmio, __oa_regs(stream)->oa_buffer, oa_buf);

drivers/gpu/drm/xe/xe_oa.c

448

xe_mmio_write32(mmio, __oa_regs(stream)->oa_tail_ptr,

drivers/gpu/drm/xe/xe_oa.c

522

xe_mmio_write32(mmio, OA_TLB_INV_CR, 1);

drivers/gpu/drm/xe/xe_oa.c

812

xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_ctrl,

drivers/gpu/drm/xe/xe_oa.c

854

xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,

drivers/gpu/drm/xe/xe_pat.c

337

xe_mmio_write32(&gt->mmio, reg, table[i].value);

drivers/gpu/drm/xe/xe_pat.c

341

xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);

drivers/gpu/drm/xe/xe_pat.c

344

xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), pta_entry->value);

drivers/gpu/drm/xe/xe_pcode.c

83

xe_mmio_write32(mmio, PCODE_DATA0, *data0);

drivers/gpu/drm/xe/xe_pcode.c

84

xe_mmio_write32(mmio, PCODE_DATA1, data1 ? *data1 : 0);

drivers/gpu/drm/xe/xe_pcode.c

85

xe_mmio_write32(mmio, PCODE_MAILBOX, PCODE_READY | mbox);

drivers/gpu/drm/xe/xe_pxp.c

153

xe_mmio_write32(&gt->mmio, KCR_GLOBAL_TERMINATE, 1);

drivers/gpu/drm/xe/xe_pxp.c

324

xe_mmio_write32(&pxp->gt->mmio, KCR_INIT, val);

drivers/gpu/drm/xe/xe_reg_sr.c

201

xe_mmio_write32(&gt->mmio, reg, val);

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

174

xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg);

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

75

xe_mmio_write32(sc->mmio, regs[i], val[i]);

drivers/gpu/drm/xe/xe_uc_fw.c

877

xe_mmio_write32(mmio, DMA_ADDR_0_LOW, lower_32_bits(src_offset));

drivers/gpu/drm/xe/xe_uc_fw.c

878

xe_mmio_write32(mmio, DMA_ADDR_0_HIGH,

drivers/gpu/drm/xe/xe_uc_fw.c

882

xe_mmio_write32(mmio, DMA_ADDR_1_LOW, offset);

drivers/gpu/drm/xe/xe_uc_fw.c

883

xe_mmio_write32(mmio, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);

drivers/gpu/drm/xe/xe_uc_fw.c

889

xe_mmio_write32(mmio, DMA_COPY_SIZE,

drivers/gpu/drm/xe/xe_uc_fw.c

893

xe_mmio_write32(mmio, DMA_CTRL,

drivers/gpu/drm/xe/xe_uc_fw.c

904

xe_mmio_write32(mmio, DMA_CTRL, REG_MASKED_FIELD_DISABLE(dma_flags));