drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

98

return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set);

drivers/gpu/drm/xe/xe_device.c

654

xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR);

drivers/gpu/drm/xe/xe_gsc.c

591

xe_mmio_rmw32(&gt->mmio, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set);

drivers/gpu/drm/xe/xe_gsc.c

595

xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE),

drivers/gpu/drm/xe/xe_gsc_proxy.c

93

xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set);

drivers/gpu/drm/xe/xe_gt.c

164

xe_mmio_rmw32(&gt->mmio, XE2_GAMWALK_CTRL_MEDIA, 0, EN_CMP_1WCOH_GW);

drivers/gpu/drm/xe/xe_guc.c

1024

xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0);

drivers/gpu/drm/xe/xe_guc.c

1385

xe_mmio_rmw32(&gt->mmio, GUC_SG_INTR_MASK, events, 0);

drivers/gpu/drm/xe/xe_guc.c

947

xe_mmio_rmw32(&gt->mmio, GUC_MAX_IDLE_COUNT, 0, GUC_IDLE_FLOW_DISABLE);

drivers/gpu/drm/xe/xe_hwmon.c

405

reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);

drivers/gpu/drm/xe/xe_hwmon.c

454

reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM, reg_val);

drivers/gpu/drm/xe/xe_hwmon.c

666

r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),

drivers/gpu/drm/xe/xe_i2c.c

191

xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_INTX_DISABLE);

drivers/gpu/drm/xe/xe_i2c.c

193

xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, PCI_COMMAND_INTX_DISABLE, 0);

drivers/gpu/drm/xe/xe_i2c.c

203

xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_INTX_DISABLE);

drivers/gpu/drm/xe/xe_i2c.c

204

xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, ACPI_INTR_EN, 0);

drivers/gpu/drm/xe/xe_i2c.c

214

xe_mmio_rmw32(mmio, I2C_BRIDGE_PCICFGCTL, 0, ACPI_INTR_EN);

drivers/gpu/drm/xe/xe_i2c.c

215

xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, PCI_COMMAND_INTX_DISABLE, 0);

drivers/gpu/drm/xe/xe_i2c.c

290

xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D3hot);

drivers/gpu/drm/xe/xe_i2c.c

302

xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);

drivers/gpu/drm/xe/xe_i2c.c

304

xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0);

drivers/gpu/drm/xe/xe_mmio.h

24

u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);

drivers/gpu/drm/xe/xe_oa.c

1151

xe_mmio_rmw32(mmio, XELPMP_SQCNT1, 0, sqcnt1);

drivers/gpu/drm/xe/xe_oa.c

1156

xe_mmio_rmw32(mmio, OAM_COMPRESSION_T3_CONTROL, 0, OAM_LAT_MEASURE_ENABLE);

drivers/gpu/drm/xe/xe_oa.c

507

xe_mmio_rmw32(&stream->gt->mmio, regs->oa_ctrl, __oactrl_used_bits(stream), val);

drivers/gpu/drm/xe/xe_oa.c

514

xe_mmio_rmw32(mmio, __oa_regs(stream)->oa_ctrl, __oactrl_used_bits(stream), 0);

drivers/gpu/drm/xe/xe_oa.c

546

stream->oa_status = xe_mmio_rmw32(&stream->gt->mmio, __oa_regs(stream)->oa_status,

drivers/gpu/drm/xe/xe_oa.c

863

xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);

drivers/gpu/drm/xe/xe_oa.c

869

xe_mmio_rmw32(mmio, XELPMP_SQCNT1, sqcnt1, 0);

drivers/gpu/drm/xe/xe_oa.c

874

xe_mmio_rmw32(mmio, OAM_COMPRESSION_T3_CONTROL, OAM_LAT_MEASURE_ENABLE, 0);

drivers/gpu/drm/xe/xe_soc_remapper.c

15

xe_mmio_rmw32(xe_root_tile_mmio(xe), reg, mask, val);

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

103

xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);

drivers/gpu/drm/xe/xe_wa.c

1028

xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);