wrmsrq_on_cpu
wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, arch_pebs_base);
wrmsrq_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0);
wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, (u64)(unsigned long)ds);
wrmsrq_on_cpu(cpu, MSR_IA32_DS_AREA, 0);
return wrmsrq_on_cpu(cpu, msr, 0);
int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
wrmsrq_on_cpu(0, msr_no, raw_cpu_read(msrs->q));
ret = wrmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS,
err = wrmsrq_on_cpu(cpu, MSR_K7_HWCR, val.q);
EXPORT_SYMBOL(wrmsrq_on_cpu);
int ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value);
wrmsrq_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q & ~(1ULL << 4));
wrmsrq_on_cpu(cpu, MSR_IA32_THERM_CONTROL, val.q);
wrmsrq_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr.q);
wrmsrq_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr.q);
ret = wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0);
return wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_HRST, 0x1);
wrmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT,
ret = wrmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, cap);
return wrmsrq_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, v.q);