writelfl
writelfl(mask, hpriv->main_irq_mask_addr);
writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
writelfl(0, port_mmio + FIS_IRQ_CAUSE);
writelfl(EDMA_EN, port_mmio + EDMA_CMD);
writelfl(EDMA_DS, port_mmio + EDMA_CMD);
writelfl(lp_phy_val, lp_phy_addr);
writelfl(val, addr);
writelfl(cfg, port_mmio + EDMA_CFG);
writelfl(pp->sg_tbl_dma[qc->hw_tag],
writelfl(cmd, port_mmio + BMDMA_CMD);
writelfl(cmd, port_mmio + BMDMA_CMD);
writelfl(ifctl, port_mmio + SATA_IFCTL);
writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
writelfl(old_ifctl, port_mmio + SATA_IFCTL);
writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
writelfl(0, mmio + hpriv->irq_cause_offset);
writelfl(val, addr + ofs);
writelfl(ifcfg, port_mmio + SATA_IFCFG);
writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
writelfl(0, port_mmio + EDMA_CMD);
writelfl(reg, port_mmio + SATA_IFCTL);
writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
writelfl(readl(serr), serr);
writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
writelfl(0, hc_mmio + HC_IRQ_CAUSE);
writelfl(0, mmio + hpriv->irq_cause_offset);
writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
writelfl(new, addr); /* read after write */
writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,