write_register
.write_register = amdgpu_cgs_write_register,
cgs_write_register_t write_register;
CGS_CALL(write_register, dev, offset, value)
write_register(reg->vaddr, val, reg->gas->bit_width);
status = write_register(state, 0x90720000, 1);
status = write_register(state, 0x9076B510, 1);
status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
stat = write_register(state, reg, data);
write_register(state, HYDRA_CRYSTAL_SETTING, 0);
write_register(state, HYDRA_CRYSTAL_SETTING, 1);
write_register(state, HYDRA_CRYSTAL_CAP, cap);
status = write_register(state, FW_DL_SIGN_ADDR, 0);
write_register(state, 0x90720000, 0);
status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
status = write_register(state, HYDRA_RESET_BBAND_REG,
status = write_register(state, HYDRA_RESET_XBAR_REG,
status = write_register(state, HYDRA_MODULES_CLK_2_REG,
#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES)
#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO)
write_register(gspca_dev, 0x105, 0x00);
write_register(gspca_dev, 0x05, 0x00);
write_register(gspca_dev, 0x13, 0x01);
write_register(gspca_dev, 0x14, 0x1e);
write_register(gspca_dev, 0x06, 0x02);
write_register(gspca_dev, 0x06, 0x00);
write_register(gspca_dev, fmt_reg, fmt_val);
write_register(gspca_dev, res_reg, res_val);
write_register(gspca_dev, fps_reg, fps_val);
write_register(gspca_dev, 0x05, mode_val);
write_register(gspca_dev, 0x47, 0x00);
write_register(gspca_dev, 0x105, 0x00);
write_register(gspca_dev, 0x06, 0x00);
write_register(gspca_dev, 0x12, 0x02);
write_register(gspca_dev, 0x13, 0x01);
write_register(gspca_dev, 0x14, 0x1e);
write_register(gspca_dev, 0x06, 0x02);
write_register(gspca_dev, 0x17, 0x00);
write_register(gspca_dev, 0x05, 0x00);
write_register(gspca_dev, 0x06, 0x00);
write_register(priv->net_dev, IPW_REG_RESET_REG, 0);
write_register(priv->net_dev, IPW_REG_INTA_MASK, IPW_INTERRUPT_MASK);
write_register(priv->net_dev, IPW_REG_INTA_MASK, 0x0);
write_register(priv->net_dev, IPW_REG_GPIO, reg);
write_register(priv->net_dev, IPW_REG_RESET_REG, 0);
write_register(priv->net_dev, IPW_REG_INTA,
write_register(priv->net_dev, IPW_REG_INTA,
write_register(priv->net_dev, IPW_REG_INTA, inta);
write_register(priv->net_dev, IPW_REG_GPIO, gpio);
write_register(priv->net_dev, IPW_REG_RESET_REG,
write_register(priv->net_dev, IPW_REG_RESET_REG,
write_register(priv->net_dev, IPW_REG_RESET_REG,
write_register(priv->net_dev, IPW_REG_RESET_REG,
write_register(priv->net_dev, IPW_REG_RESET_REG,
write_register(priv->net_dev,
write_register(priv->net_dev,
write_register(priv->net_dev,
write_register(dev, IPW_REG_INTA, IPW2100_INTA_FATAL_ERROR);
write_register(dev, IPW_REG_INTA, IPW2100_INTA_PARITY_ERROR);
write_register(dev, IPW_REG_INTA, IPW2100_INTA_RX_TRANSFER);
write_register(dev, IPW_REG_INTA, IPW2100_INTA_TX_TRANSFER);
write_register(dev, IPW_REG_INTA, IPW2100_INTA_TX_COMPLETE);
write_register(dev, IPW_REG_INTA, IPW2100_INTA_EVENT_INTERRUPT);
write_register(dev, IPW_REG_INTA,
write_register(dev, IPW_REG_INTA, IPW2100_INTA_FW_INIT_DONE);
write_register(dev, IPW_REG_INTA, IPW2100_INTA_STATUS_CHANGE);
write_register(dev, IPW_REG_INTA,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(priv->net_dev, base, q->nic);
write_register(priv->net_dev, size, q->entries);
write_register(priv->net_dev, r, q->oldest);
write_register(priv->net_dev, w, q->next);
write_register(dev, IPW_REG_AUTOINCREMENT_ADDRESS, aligned_addr);
write_register(dev, IPW_REG_AUTOINCREMENT_DATA, *(u32 *) buf);
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS, aligned_addr);
write_register(priv->net_dev, IPW_MEM_HOST_SHARED_RX_STATUS_BASE,
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
write_register(dev, IPW_REG_AUTOINCREMENT_ADDRESS, aligned_addr);
write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS, aligned_addr);
write_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x32,
write_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x36,
write_register(priv->net_dev, IPW_REG_RESET_REG,
write_register(priv->net_dev, IPW_REG_GP_CNTRL,
write_register(priv->net_dev, IPW_REG_GP_CNTRL,
.write_register = write_reg8_bus8,
.write_register = write_reg8_bus8,
.write_register = write_register,
.write_register = write_reg8_bus8,
par->fbtftops.write_register = fbtft_write_reg8_bus8;
par->fbtftops.write_register = fbtft_write_reg8_bus9;
par->fbtftops.write_register = fbtft_write_reg16_bus8;
par->fbtftops.write_register = fbtft_write_reg16_bus16;
if (src->write_register)
dst->write_register = src->write_register;
par->fbtftops.write_register = fbtft_write_reg8_bus8;
par->fbtftops.write_register(par, i,
par->fbtftops.write_register(par, j,
((par)->fbtftops.write_register(par, NUMARGS(__VA_ARGS__), __VA_ARGS__))
void (*write_register)(struct fbtft_par *par, int len, ...);