xr_set_reg_uart
ret = xr_set_reg_uart(port, type->gpio_direction, mask);
ret = xr_set_reg_uart(port, type->gpio_set, mask);
ret = xr_set_reg_uart(port, type->custom_driver,
return xr_set_reg_uart(port, data->type->uart_enable,
return xr_set_reg_uart(port, data->type->uart_enable, 0);
ret = xr_set_reg_uart(port, data->type->tx_fifo_reset, XR_FIFO_RESET);
ret = xr_set_reg_uart(port, data->type->rx_fifo_reset, XR_FIFO_RESET);
ret = xr_set_reg_uart(port, type->gpio_clear, gpio_clr);
ret = xr_set_reg_uart(port, type->gpio_set, gpio_set);
return xr_set_reg_uart(port, type->tx_break, state);
ret = xr_set_reg_uart(port, XR21V141X_CLOCK_DIVISOR_0,
ret = xr_set_reg_uart(port, XR21V141X_CLOCK_DIVISOR_1,
ret = xr_set_reg_uart(port, XR21V141X_CLOCK_DIVISOR_2,
ret = xr_set_reg_uart(port, XR21V141X_TX_CLOCK_MASK_0,
ret = xr_set_reg_uart(port, XR21V141X_TX_CLOCK_MASK_1,
ret = xr_set_reg_uart(port, XR21V141X_RX_CLOCK_MASK_0,
ret = xr_set_reg_uart(port, XR21V141X_RX_CLOCK_MASK_1,
xr_set_reg_uart(port, type->xon_char, start_char);
xr_set_reg_uart(port, type->xoff_char, stop_char);
xr_set_reg_uart(port, type->flow_control, flow);
xr_set_reg_uart(port, type->gpio_mode, gpio_mode);
ret = xr_set_reg_uart(port, XR21V141X_REG_FORMAT, bits);
ret = xr_set_reg_uart(port, type->gpio_mode, mode);