Symbol: write_csr
drivers/firewire/core-card.c
756
.write_csr = dummy_write_csr,
drivers/firewire/core-transaction.c
1322
card->driver->write_csr(card, reg, be32_to_cpu(*data));
drivers/firewire/core-transaction.c
1329
card->driver->write_csr(card, CSR_STATE_CLEAR,
drivers/firewire/core.h
100
void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
drivers/firewire/ohci.c
3519
.write_csr = ohci_write_csr,
drivers/infiniband/hw/hfi1/chip.c
10131
write_csr(dd, SEND_LEN_CHECK0, len1);
drivers/infiniband/hw/hfi1/chip.c
10132
write_csr(dd, SEND_LEN_CHECK1, len2);
drivers/infiniband/hw/hfi1/chip.c
10158
write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
drivers/infiniband/hw/hfi1/chip.c
10181
write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
drivers/infiniband/hw/hfi1/chip.c
10360
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
drivers/infiniband/hw/hfi1/chip.c
10361
write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
drivers/infiniband/hw/hfi1/chip.c
10364
write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
drivers/infiniband/hw/hfi1/chip.c
10365
write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
drivers/infiniband/hw/hfi1/chip.c
10366
write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
drivers/infiniband/hw/hfi1/chip.c
10367
write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
drivers/infiniband/hw/hfi1/chip.c
10369
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
drivers/infiniband/hw/hfi1/chip.c
10372
write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
drivers/infiniband/hw/hfi1/chip.c
10373
write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
drivers/infiniband/hw/hfi1/chip.c
10380
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
drivers/infiniband/hw/hfi1/chip.c
10381
write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
drivers/infiniband/hw/hfi1/chip.c
10382
write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
drivers/infiniband/hw/hfi1/chip.c
10457
write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
drivers/infiniband/hw/hfi1/chip.c
10813
write_csr(dd, DCC_CFG_LED_CNTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
10977
write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
drivers/infiniband/hw/hfi1/chip.c
11149
write_csr(dd, target + (i * 8), reg);
drivers/infiniband/hw/hfi1/chip.c
11245
write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
drivers/infiniband/hw/hfi1/chip.c
11263
write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
drivers/infiniband/hw/hfi1/chip.c
11299
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
11310
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
11327
write_csr(dd, addr, reg);
drivers/infiniband/hw/hfi1/chip.c
11344
write_csr(dd, addr, reg);
drivers/infiniband/hw/hfi1/chip.c
12067
write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
drivers/infiniband/hw/hfi1/chip.c
12070
write_csr(dd, RCV_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
13169
write_csr(dd, CCE_INT_MASK + (8 * idx), reg);
drivers/infiniband/hw/hfi1/chip.c
13216
write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13218
write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13219
write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13220
write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13221
write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13222
write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13223
write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13224
write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13230
write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13231
write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13232
write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13260
write_csr(dd, CCE_INT_MAP + (8 * m), reg);
drivers/infiniband/hw/hfi1/chip.c
13291
write_csr(dd, CCE_INT_MAP + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
1349
write_csr(dd, csr, value);
drivers/infiniband/hw/hfi1/chip.c
13514
write_csr(dd, RCV_PARTITION_KEY +
drivers/infiniband/hw/hfi1/chip.c
13538
write_csr(dd, CCE_INT_MAP + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13567
write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13585
write_csr(dd, CCE_CTRL, ctrl_bits);
drivers/infiniband/hw/hfi1/chip.c
13616
write_csr(dd, CCE_SCRATCH + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13618
write_csr(dd, CCE_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13619
write_csr(dd, CCE_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13622
write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13623
write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
drivers/infiniband/hw/hfi1/chip.c
13626
write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13627
write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
drivers/infiniband/hw/hfi1/chip.c
13632
write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13633
write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13636
write_csr(dd, CCE_INT_MAP, 0);
drivers/infiniband/hw/hfi1/chip.c
13639
write_csr(dd, CCE_INT_MASK + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13640
write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13645
write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13654
write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13655
write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13656
write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13663
write_csr(dd, MISC_CFG_RSA_CMD, 1);
drivers/infiniband/hw/hfi1/chip.c
13664
write_csr(dd, MISC_CFG_RSA_MU, 0);
drivers/infiniband/hw/hfi1/chip.c
13665
write_csr(dd, MISC_CFG_FW_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13671
write_csr(dd, MISC_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13672
write_csr(dd, MISC_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13684
write_csr(dd, SEND_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13690
write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
drivers/infiniband/hw/hfi1/chip.c
13693
write_csr(dd, SEND_PIO_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13694
write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13697
write_csr(dd, SEND_DMA_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13698
write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13701
write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13702
write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13704
write_csr(dd, SEND_BTH_QP, 0);
drivers/infiniband/hw/hfi1/chip.c
13705
write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
drivers/infiniband/hw/hfi1/chip.c
13706
write_csr(dd, SEND_SC2VLT0, 0);
drivers/infiniband/hw/hfi1/chip.c
13707
write_csr(dd, SEND_SC2VLT1, 0);
drivers/infiniband/hw/hfi1/chip.c
13708
write_csr(dd, SEND_SC2VLT2, 0);
drivers/infiniband/hw/hfi1/chip.c
13709
write_csr(dd, SEND_SC2VLT3, 0);
drivers/infiniband/hw/hfi1/chip.c
13710
write_csr(dd, SEND_LEN_CHECK0, 0);
drivers/infiniband/hw/hfi1/chip.c
13711
write_csr(dd, SEND_LEN_CHECK1, 0);
drivers/infiniband/hw/hfi1/chip.c
13713
write_csr(dd, SEND_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13714
write_csr(dd, SEND_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13717
write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13719
write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13721
write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13723
write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13725
write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13726
write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
drivers/infiniband/hw/hfi1/chip.c
13727
write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
drivers/infiniband/hw/hfi1/chip.c
13729
write_csr(dd, SEND_CM_TIMER_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13730
write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
drivers/infiniband/hw/hfi1/chip.c
13731
write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
drivers/infiniband/hw/hfi1/chip.c
13732
write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
drivers/infiniband/hw/hfi1/chip.c
13733
write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
drivers/infiniband/hw/hfi1/chip.c
13735
write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13736
write_csr(dd, SEND_CM_CREDIT_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
13741
write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13829
write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
drivers/infiniband/hw/hfi1/chip.c
13866
write_csr(dd, RCV_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13872
write_csr(dd, RCV_BTH_QP, 0);
drivers/infiniband/hw/hfi1/chip.c
13873
write_csr(dd, RCV_MULTICAST, 0);
drivers/infiniband/hw/hfi1/chip.c
13874
write_csr(dd, RCV_BYPASS, 0);
drivers/infiniband/hw/hfi1/chip.c
13875
write_csr(dd, RCV_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
13877
write_csr(dd, RCV_ERR_INFO,
drivers/infiniband/hw/hfi1/chip.c
13880
write_csr(dd, RCV_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13881
write_csr(dd, RCV_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13884
write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13886
write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13888
write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13890
write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13894
write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13944
write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13950
write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13956
write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13962
write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13970
write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13974
write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
14014
write_csr(dd, SEND_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14020
write_csr(dd, RCV_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14022
write_csr(dd, RCV_CTXT_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14025
write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
drivers/infiniband/hw/hfi1/chip.c
14033
write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
drivers/infiniband/hw/hfi1/chip.c
14073
write_csr(dd, CCE_DC_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14088
write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
drivers/infiniband/hw/hfi1/chip.c
14089
write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
drivers/infiniband/hw/hfi1/chip.c
14122
write_csr(dd, SEND_BTH_QP,
drivers/infiniband/hw/hfi1/chip.c
14126
write_csr(dd, RCV_BTH_QP,
drivers/infiniband/hw/hfi1/chip.c
14176
write_csr(dd, regno, reg);
drivers/infiniband/hw/hfi1/chip.c
14236
write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
drivers/infiniband/hw/hfi1/chip.c
14255
write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
drivers/infiniband/hw/hfi1/chip.c
14259
write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
drivers/infiniband/hw/hfi1/chip.c
14266
write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
drivers/infiniband/hw/hfi1/chip.c
14278
write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
drivers/infiniband/hw/hfi1/chip.c
14279
write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
drivers/infiniband/hw/hfi1/chip.c
14280
write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
drivers/infiniband/hw/hfi1/chip.c
14531
write_csr(dd, regoff, reg);
drivers/infiniband/hw/hfi1/chip.c
14594
write_csr(dd, RCV_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14625
write_csr(dd, RCV_BYPASS, val);
drivers/infiniband/hw/hfi1/chip.c
14632
write_csr(dd, CCE_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14634
write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
drivers/infiniband/hw/hfi1/chip.c
14636
write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14637
write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14651
write_csr(dd, csr0to3,
drivers/infiniband/hw/hfi1/chip.c
14658
write_csr(dd, csr4to7,
drivers/infiniband/hw/hfi1/chip.c
14686
write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14687
write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14688
write_csr(dd, SEND_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14689
write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14705
write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
drivers/infiniband/hw/hfi1/chip.c
14907
write_csr(dd, CCE_INT_MASK, 0ull);
drivers/infiniband/hw/hfi1/chip.c
14913
write_csr(dd, CCE_INT_CLEAR, all_bits);
drivers/infiniband/hw/hfi1/chip.c
14919
write_csr(dd, CCE_INT_FORCE, all_bits);
drivers/infiniband/hw/hfi1/chip.c
14925
write_csr(dd, CCE_INT_CLEAR, all_bits);
drivers/infiniband/hw/hfi1/chip.c
14926
write_csr(dd, CCE_INT_MASK, mask);
drivers/infiniband/hw/hfi1/chip.c
14930
write_csr(dd, CCE_INT_MASK, mask);
drivers/infiniband/hw/hfi1/chip.c
15357
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
drivers/infiniband/hw/hfi1/chip.c
15400
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
drivers/infiniband/hw/hfi1/chip.c
5675
write_csr(dd, SEND_EGRESS_ERR_INFO, info);
drivers/infiniband/hw/hfi1/chip.c
6091
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
drivers/infiniband/hw/hfi1/chip.c
6127
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
drivers/infiniband/hw/hfi1/chip.c
6182
write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
drivers/infiniband/hw/hfi1/chip.c
6193
write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
drivers/infiniband/hw/hfi1/chip.c
6317
write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
drivers/infiniband/hw/hfi1/chip.c
6339
write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
drivers/infiniband/hw/hfi1/chip.c
6360
write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET);
drivers/infiniband/hw/hfi1/chip.c
6366
write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
drivers/infiniband/hw/hfi1/chip.c
6394
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
6415
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
6417
write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
drivers/infiniband/hw/hfi1/chip.c
6431
write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
6432
write_csr(dd, SEND_CM_CREDIT_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
6433
write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
drivers/infiniband/hw/hfi1/chip.c
6472
write_csr(dd, DC_LCB_CFG_RUN, 0);
drivers/infiniband/hw/hfi1/chip.c
6474
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
drivers/infiniband/hw/hfi1/chip.c
6479
write_csr(dd, DCC_CFG_RESET, reg |
drivers/infiniband/hw/hfi1/chip.c
6484
write_csr(dd, DCC_CFG_RESET, reg);
drivers/infiniband/hw/hfi1/chip.c
6485
write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
drivers/infiniband/hw/hfi1/chip.c
6514
write_csr(dd, DC_DC8051_CFG_RST, 0x1);
drivers/infiniband/hw/hfi1/chip.c
6538
write_csr(dd, DC_DC8051_CFG_RST, 0ull);
drivers/infiniband/hw/hfi1/chip.c
6545
write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
drivers/infiniband/hw/hfi1/chip.c
6547
write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
drivers/infiniband/hw/hfi1/chip.c
6625
write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
drivers/infiniband/hw/hfi1/chip.c
6636
write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
drivers/infiniband/hw/hfi1/chip.c
6638
write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
drivers/infiniband/hw/hfi1/chip.c
6640
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
drivers/infiniband/hw/hfi1/chip.c
6713
write_csr(dd, RCV_CTRL, rcvctrl);
drivers/infiniband/hw/hfi1/chip.c
6738
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
6887
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
6891
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
6893
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
7491
write_csr(dd, DC_LCB_CFG_CRC_MODE,
drivers/infiniband/hw/hfi1/chip.c
7497
write_csr(dd, SEND_CM_CTRL,
drivers/infiniband/hw/hfi1/chip.c
7500
write_csr(dd, SEND_CM_CTRL,
drivers/infiniband/hw/hfi1/chip.c
7561
write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
drivers/infiniband/hw/hfi1/chip.c
7565
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
drivers/infiniband/hw/hfi1/chip.c
7568
write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
drivers/infiniband/hw/hfi1/chip.c
7836
write_csr(dd, DC_DC8051_ERR_EN,
drivers/infiniband/hw/hfi1/chip.c
8299
write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
drivers/infiniband/hw/hfi1/chip.c
8332
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
8355
write_csr(dd, addr, rcd->imask);
drivers/infiniband/hw/hfi1/chip.c
8363
write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
drivers/infiniband/hw/hfi1/chip.c
8556
write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
drivers/infiniband/hw/hfi1/chip.c
8664
write_csr(dd, addr, data);
drivers/infiniband/hw/hfi1/chip.c
8694
write_csr(dd, addr, data);
drivers/infiniband/hw/hfi1/chip.c
8767
write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
drivers/infiniband/hw/hfi1/chip.c
8778
write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
drivers/infiniband/hw/hfi1/chip.c
8780
write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
drivers/infiniband/hw/hfi1/chip.c
8817
write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
drivers/infiniband/hw/hfi1/chip.c
9191
write_csr(dd, DC_LCB_CFG_LOOPBACK,
drivers/infiniband/hw/hfi1/chip.c
9193
write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
drivers/infiniband/hw/hfi1/chip.c
9198
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
drivers/infiniband/hw/hfi1/chip.c
9203
write_csr(dd, DC_LCB_CFG_RUN,
drivers/infiniband/hw/hfi1/chip.c
9210
write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
drivers/infiniband/hw/hfi1/chip.c
9228
write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
drivers/infiniband/hw/hfi1/chip.c
9243
write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
drivers/infiniband/hw/hfi1/chip.c
9261
write_csr(dd, DC_DC8051_CFG_MODE,
drivers/infiniband/hw/hfi1/chip.c
9503
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
drivers/infiniband/hw/hfi1/chip.c
9509
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
drivers/infiniband/hw/hfi1/chip.c
9526
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
9532
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
9720
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
drivers/infiniband/hw/hfi1/chip.c
9722
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
drivers/infiniband/hw/hfi1/chip.c
9730
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
9753
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
drivers/infiniband/hw/hfi1/chip.c
9754
write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
drivers/infiniband/hw/hfi1/chip.c
9755
write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
drivers/infiniband/hw/hfi1/chip.c
9756
write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
drivers/infiniband/hw/hfi1/chip.c
9757
write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
drivers/infiniband/hw/hfi1/chip.c
9758
write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
drivers/infiniband/hw/hfi1/chip.c
9759
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
drivers/infiniband/hw/hfi1/chip.h
576
void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
drivers/infiniband/hw/hfi1/chip.h
594
write_csr(dd, offset0 + (0x100 * ctxt), value);
drivers/infiniband/hw/hfi1/chip.h
629
write_csr(dd, offset0 + (0x1000 * ctxt), value);
drivers/infiniband/hw/hfi1/debugfs.c
1012
write_csr(dd, ASIC_GPIO_OUT, gpio_val);
drivers/infiniband/hw/hfi1/debugfs.c
1013
write_csr(dd, ASIC_GPIO_OE, gpio_val);
drivers/infiniband/hw/hfi1/debugfs.c
551
write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
drivers/infiniband/hw/hfi1/driver.c
1312
write_csr(dd, DCC_CFG_LED_CNTRL, 0);
drivers/infiniband/hw/hfi1/eprom.c
152
write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
drivers/infiniband/hw/hfi1/eprom.c
154
write_csr(dd, ASIC_EEP_CTL_STAT,
drivers/infiniband/hw/hfi1/eprom.c
158
write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
drivers/infiniband/hw/hfi1/eprom.c
51
write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset));
drivers/infiniband/hw/hfi1/eprom.c
54
write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */
drivers/infiniband/hw/hfi1/firmware.c
1000
write_csr(dd, DC_DC8051_CFG_RST, 0ull);
drivers/infiniband/hw/hfi1/firmware.c
1036
write_csr(dd, ASIC_CFG_SBUS_REQUEST,
drivers/infiniband/hw/hfi1/firmware.c
1100
write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
drivers/infiniband/hw/hfi1/firmware.c
1110
write_csr(dd, MISC_CFG_FW_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
1180
write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
drivers/infiniband/hw/hfi1/firmware.c
1203
write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
drivers/infiniband/hw/hfi1/firmware.c
1369
write_csr(dd, ASIC_CFG_MUTEX, mask);
drivers/infiniband/hw/hfi1/firmware.c
1385
write_csr(dd, ASIC_CFG_MUTEX, 0);
drivers/infiniband/hw/hfi1/firmware.c
1403
write_csr(dd, ASIC_CFG_MUTEX, 0);
drivers/infiniband/hw/hfi1/firmware.c
1462
write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit);
drivers/infiniband/hw/hfi1/firmware.c
1524
write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
drivers/infiniband/hw/hfi1/firmware.c
1578
write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
drivers/infiniband/hw/hfi1/firmware.c
1602
write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
drivers/infiniband/hw/hfi1/firmware.c
1618
write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
drivers/infiniband/hw/hfi1/firmware.c
2165
write_csr(dd, CCE_DC_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
237
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
drivers/infiniband/hw/hfi1/firmware.c
239
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
drivers/infiniband/hw/hfi1/firmware.c
274
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
drivers/infiniband/hw/hfi1/firmware.c
283
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
306
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
drivers/infiniband/hw/hfi1/firmware.c
311
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
drivers/infiniband/hw/hfi1/firmware.c
325
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
drivers/infiniband/hw/hfi1/firmware.c
342
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
343
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
drivers/infiniband/hw/hfi1/firmware.c
745
write_csr(dd, what + (8 * i), *ptr);
drivers/infiniband/hw/hfi1/firmware.c
752
write_csr(dd, what + (8 * i), value);
drivers/infiniband/hw/hfi1/firmware.c
768
write_csr(dd, what, *ptr);
drivers/infiniband/hw/hfi1/firmware.c
787
write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
drivers/infiniband/hw/hfi1/firmware.c
803
write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
drivers/infiniband/hw/hfi1/firmware.c
868
write_csr(dd, MISC_ERR_CLEAR,
drivers/infiniband/hw/hfi1/firmware.c
958
write_csr(dd, DC_DC8051_CFG_RST, reg);
drivers/infiniband/hw/hfi1/firmware.c
970
write_csr(dd, DC_DC8051_CFG_RST, reg);
drivers/infiniband/hw/hfi1/firmware.c
978
write_csr(dd, MISC_CFG_FW_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
992
write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
drivers/infiniband/hw/hfi1/hfi.h
2349
write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
drivers/infiniband/hw/hfi1/hfi.h
2351
write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
drivers/infiniband/hw/hfi1/init.c
531
write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
drivers/infiniband/hw/hfi1/mad.c
1761
write_csr(dd, SEND_SC2VLT0, *val++);
drivers/infiniband/hw/hfi1/mad.c
1762
write_csr(dd, SEND_SC2VLT1, *val++);
drivers/infiniband/hw/hfi1/mad.c
1763
write_csr(dd, SEND_SC2VLT2, *val++);
drivers/infiniband/hw/hfi1/mad.c
1764
write_csr(dd, SEND_SC2VLT3, *val++);
drivers/infiniband/hw/hfi1/mad.c
3630
write_csr(dd, RCV_ERR_INFO,
drivers/infiniband/hw/hfi1/pcie.c
1022
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
drivers/infiniband/hw/hfi1/pcie.c
1234
write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
drivers/infiniband/hw/hfi1/pcie.c
1289
write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
drivers/infiniband/hw/hfi1/pcie.c
1311
write_csr(dd, CCE_DC_CTRL, 0);
drivers/infiniband/hw/hfi1/pcie.c
1367
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
drivers/infiniband/hw/hfi1/pcie.c
831
write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
drivers/infiniband/hw/hfi1/pcie.c
850
write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
drivers/infiniband/hw/hfi1/pcie.c
925
write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
drivers/infiniband/hw/hfi1/pio.c
1225
write_csr(dd, SEND_PIO_ERR_CLEAR,
drivers/infiniband/hw/hfi1/pio.c
1230
write_csr(dd, SEND_PIO_INIT_CTXT,
drivers/infiniband/hw/hfi1/pio.c
1303
write_csr(dd, SEND_PIO_INIT_CTXT, pio);
drivers/infiniband/hw/hfi1/pio.c
23
write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
drivers/infiniband/hw/hfi1/pio.c
81
write_csr(dd, SEND_CTRL, reg);
drivers/infiniband/hw/hfi1/qsfp.c
43
write_csr(dd, target_oe, reg);
drivers/infiniband/hw/hfi1/qsfp.c
67
write_csr(dd, target_oe, reg);
drivers/infiniband/hw/hfi1/sdma.c
3363
write_csr(sde->dd,
drivers/net/ethernet/amd/pcnet32.c
1006
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
drivers/net/ethernet/amd/pcnet32.c
1057
lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
drivers/net/ethernet/amd/pcnet32.c
1060
lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
drivers/net/ethernet/amd/pcnet32.c
1079
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
drivers/net/ethernet/amd/pcnet32.c
1115
a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
drivers/net/ethernet/amd/pcnet32.c
1406
lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
drivers/net/ethernet/amd/pcnet32.c
1417
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
1420
lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
drivers/net/ethernet/amd/pcnet32.c
1721
a->write_csr(ioaddr, 80,
drivers/net/ethernet/amd/pcnet32.c
1922
a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
drivers/net/ethernet/amd/pcnet32.c
1923
a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
drivers/net/ethernet/amd/pcnet32.c
1938
a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
drivers/net/ethernet/amd/pcnet32.c
2155
lp->a->write_csr(ioaddr, 124, val);
drivers/net/ethernet/amd/pcnet32.c
2259
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
2275
lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
drivers/net/ethernet/amd/pcnet32.c
2276
lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
drivers/net/ethernet/amd/pcnet32.c
2278
lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
drivers/net/ethernet/amd/pcnet32.c
2279
lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
drivers/net/ethernet/amd/pcnet32.c
2297
lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
drivers/net/ethernet/amd/pcnet32.c
243
void (*write_csr) (unsigned long, int, u16);
drivers/net/ethernet/amd/pcnet32.c
2446
lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
drivers/net/ethernet/amd/pcnet32.c
2452
lp->a->write_csr(ioaddr, CSR0, csr0_bits);
drivers/net/ethernet/amd/pcnet32.c
2465
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
2544
lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
drivers/net/ethernet/amd/pcnet32.c
2575
lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
drivers/net/ethernet/amd/pcnet32.c
2608
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
2645
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
2695
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2696
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2697
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2698
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2712
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
drivers/net/ethernet/amd/pcnet32.c
2734
lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
drivers/net/ethernet/amd/pcnet32.c
2738
lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
drivers/net/ethernet/amd/pcnet32.c
2745
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
383
.write_csr = pcnet32_wio_write_csr,
drivers/net/ethernet/amd/pcnet32.c
438
.write_csr = pcnet32_dwio_write_csr,
drivers/net/ethernet/amd/pcnet32.c
464
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
690
a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
drivers/net/ethernet/amd/pcnet32.c
715
lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
drivers/net/ethernet/amd/pcnet32.c
763
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
776
lp->a->write_csr(ioaddr, CSR15, csr15);
drivers/net/ethernet/amd/pcnet32.c
894
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
drivers/net/ethernet/amd/pcnet32.c
992
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
drivers/net/ethernet/amd/pcnet32.c
998
lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */