arch/powerpc/include/asm/eeh.h

226

int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val);

arch/powerpc/kernel/eeh_pe.c

663

eeh_ops->write_config(edev, cap + PCI_EXP_SLTCTL, 2, val);

arch/powerpc/kernel/eeh_pe.c

671

eeh_ops->write_config(edev, cap + PCI_EXP_LNKCTL, 2, val);

arch/powerpc/kernel/eeh_pe.c

712

eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);

arch/powerpc/kernel/eeh_pe.c

714

eeh_ops->write_config(edev, 14*4, 4, edev->config_space[14]);

arch/powerpc/kernel/eeh_pe.c

717

eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,

arch/powerpc/kernel/eeh_pe.c

719

eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,

arch/powerpc/kernel/eeh_pe.c

722

eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);

arch/powerpc/kernel/eeh_pe.c

725

eeh_ops->write_config(edev, PCI_COMMAND, 4, edev->config_space[1] |

arch/powerpc/kernel/eeh_pe.c

738

eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]);

arch/powerpc/kernel/eeh_pe.c

740

eeh_ops->write_config(edev, 12*4, 4, edev->config_space[12]);

arch/powerpc/kernel/eeh_pe.c

742

eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1,

arch/powerpc/kernel/eeh_pe.c

744

eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1,

arch/powerpc/kernel/eeh_pe.c

748

eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]);

arch/powerpc/kernel/eeh_pe.c

763

eeh_ops->write_config(edev, PCI_COMMAND, 4, cmd);

arch/powerpc/platforms/powernv/eeh-powernv.c

1636

.write_config = pnv_eeh_write_config,

arch/powerpc/platforms/powernv/eeh-powernv.c

820

eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,

arch/powerpc/platforms/powernv/eeh-powernv.c

826

eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);

arch/powerpc/platforms/powernv/eeh-powernv.c

833

eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);

arch/powerpc/platforms/powernv/eeh-powernv.c

842

eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,

arch/powerpc/platforms/powernv/eeh-powernv.c

949

eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,

arch/powerpc/platforms/powernv/eeh-powernv.c

957

eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,

arch/powerpc/platforms/powernv/eeh-powernv.c

989

eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,

arch/powerpc/platforms/powernv/eeh-powernv.c

994

eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);

arch/powerpc/platforms/pseries/eeh_pseries.c

836

.write_config = pseries_eeh_write_config,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

122

DPU_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

72

u32 write_config = 0;

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

872

struct thc_dma_configuration *write_config = &dev->dma_ctx->dma_config[THC_TXDMA];

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

881

prd_tbl = &write_config->prd_tbls[0];

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

888

sg = write_config->sgls[0];

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

896

prd_tbl = &write_config->prd_tbls[0];

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

899

for_each_sg(write_config->sgls[0], sg, write_config->sgls_nent[0], i) {

drivers/hid/intel-thc-hid/intel-thc/intel-thc-dma.c

920

dma_set_prd_control(dev, i, 0, write_config);

drivers/pci/controller/pcie-mt7621.c

418

write_config(pcie, slot, PCIE_FTS_NUM, val);