write3X4
write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
write3X4(par, VGA_CRTC_H_SYNC_END,
write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
write3X4(par, VGA_CRTC_OVERFLOW, tmp);
write3X4(par, CRTHiOrd, tmp);
write3X4(par, HorizOverflow, tmp);
write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
write3X4(par, VGA_CRTC_PRESET_ROW, 0);
write3X4(par, VGA_CRTC_MODE, 0xC3);
write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
write3X4(par, CRTCModuleTest, tmp);
write3X4(par, GraphEngReg, 0x80);
write3X4(par, PixelBusReg, tmp);
write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
write3X4(par, Performance, read3X4(par, Performance) | 0x10);
write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
write3X4(par, VGA_CRTC_V_SYNC_END,
write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
write3X4(par, AddColReg,
write3X4(par, AddColReg,
write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));