xm_write16
xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
xm_write16(hw, port, XM_PHY_DATA, val);
xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
xm_write16(hw, port, XM_MMU_CMD, r);
xm_write16(hw, port, XM_IMSK, msk);
xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
xm_write16(hw, port, XM_STAT_CMD,
xm_write16(hw, port, XM_STAT_CMD,
xm_write16(hw, port, XM_RX_HI_WM, 1450);
xm_write16(hw, port, XM_RX_CMD, r);
xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
xm_write16(hw, port, XM_TX_THR, 1020);
xm_write16(hw, port, XM_TX_THR, 512);
xm_write16(hw, port, XM_MMU_CMD, cmd);
xm_write16(hw, port, XM_MMU_CMD,
xm_write16(hw, port,
xm_write16(hw, port, XM_MMU_CMD, cmd);
xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
xm_write16(hw, port, XM_IMSK, msk);
xm_write16(hw, port, XM_MMU_CMD,
xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));