D5
SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8);
FUNC_GROUP_DECL(TIMER8, D5);
FUNC_GROUP_DECL(MDIO2, A3, D5);
ASPEED_PINCTRL_PIN(D5),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2);
PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0),
SIG_EXPR_LIST_PTR(D5, RGMII2TXD2));
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
ASPEED_PINCTRL_PIN(D5),
SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2),
SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2),
PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0);
FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5);
ASPEED_PINCTRL_PIN(D5),
PIC32_PINCTRL_GROUP(53, D5,
PINMUX_IPSR_GPSR(IP1_31_28, D5),
PINMUX_IPSR_NOGP(IP2_23, D5),
PIN_NOGP_CFG(D5, "D5", fn, SH_PFC_PIN_CFG_PULL_UP), \
PINMUX_IPSR_GPSR(IP0_19_16, D5),
PINMUX_IPSR_GPSR(IP0_5, D5),
PINMUX_SINGLE(D5),
PINMUX_IPSR_GPSR(IP0_31_30, D5),
#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR0_5 F_(D5, IP6_3_0)
PINMUX_IPSR_GPSR(IP6_3_0, D5),
#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP6_3_0, D5),
#define GPSR0_5 F_(D5, IP6_3_0)
#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP6_3_0, D5),
#define GPSR0_5 F_(D5, IP6_3_0)
#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP5_27_24, D5),
#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP5_27_24, D5),
#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR0_5 F_(D5, IP6_11_8)
PINMUX_IPSR_GPSR(IP6_11_8, D5),
#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
GPIO_FN(D5),
GPIO_FN(D5),
GPIO_FN(D5),
GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
PINMUX_IPSR_GPSR(IP2_4_3, D5),
GPIO_FN(D5),