xive_native_configure_irq
int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
return xive_native_configure_irq(hw_num,
xive_native_configure_irq(hw_irq,
xive_native_configure_irq(state->ipi_number,
xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);
xive_native_configure_irq(state->pt_number, 0, MASKED, 0);
r = xive_native_configure_irq(xc->vp_ipi, xc->vp_id, 0, XICS_IPI);
xive_native_configure_irq(hw_num, 0, MASKED, 0);
xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);
rc = xive_native_configure_irq(hw_num,
rc = xive_native_configure_irq(hw_num, 0, MASKED, 0);
xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);
xive_native_configure_irq(state->pt_number,
EXPORT_SYMBOL_GPL(xive_native_configure_irq);
.configure_irq = xive_native_configure_irq,