xgene_enet_wr_csr
xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
xgene_enet_wr_csr(pdata, RXBUF_PAUSE_THRESH, DEF_PAUSE_THRES);
xgene_enet_wr_csr(pdata, RXBUF_PAUSE_OFF_THRESH, DEF_PAUSE_OFF_THRES);
xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
xgene_enet_wr_csr(p, debug_addr, value);
xgene_enet_wr_csr(p, enet_spare_cfg_reg, data);
xgene_enet_wr_csr(p, rsif_config_reg, data);
xgene_enet_wr_csr(p, pause_thres_reg, data1);
xgene_enet_wr_csr(p, pause_off_thres_reg, data2);
xgene_enet_wr_csr(p, pause_thres_reg, data);
xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84);
xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX);
xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data);
xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data);
xgene_enet_wr_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, data);
xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data);
xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
xgene_enet_wr_csr(pdata, XG_RXBUF_PAUSE_THRESH, data);
xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);