wlcore_write32
ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
ret = wlcore_write32(wl, addr, tmp);
ret = wlcore_write32(wl, addr - 2, tmp);
ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
ret = wlcore_write32(wl, dest_addr, val);
ret = wlcore_write32(wl, addr + WL18XX_LOGGER_READ_POINT_OFFSET,
ret = wlcore_write32(wl, WL12XX_REG_RX_DRIVER_COUNTER,
bus_ret = wlcore_write32(wl, WL12XX_HOST_WR_ACCESS,
ret = wlcore_write32(wl, le32_to_cpu(memmap->tx_result) +