D15
ASPEED_PINCTRL_PIN(D15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE);
PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN);
FUNC_GROUP_DECL(NCTS3, D15);
FUNC_GROUP_DECL(GPIE0, D15, C15);
ASPEED_PINCTRL_PIN(D15),
SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3);
FUNC_GROUP_DECL(SALT3, D15);
FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
ASPEED_PINCTRL_PIN(D15),
SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24));
PIN_DECL_1(D15, GPIOL0, SCL9);
FUNC_GROUP_DECL(I2C9, D15, A14);
PIC32_PINCTRL_GROUP(63, D15,
PINMUX_IPSR_GPSR(IP3_7_4, D15),
PIN_NOGP_CFG(D15, "D15", fn, SH_PFC_PIN_CFG_PULL_UP), \
PINMUX_IPSR_GPSR(IP1_25_22, D15),
PINMUX_IPSR_GPSR(IP0_15, D15),
PINMUX_SINGLE(D15),
PINMUX_IPSR_GPSR(IP1_21_20, D15),
PINMUX_IPSR_GPSR(IP7_11_8, D15),
#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR0_15 F_(D15, IP7_11_8)
PINMUX_IPSR_GPSR(IP7_11_8, D15),
#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR0_15 F_(D15, IP7_11_8)
PINMUX_IPSR_GPSR(IP7_11_8, D15),
#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR0_15 F_(D15, IP7_11_8)
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP7_3_0, D15),
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP7_3_0, D15),
#define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define GPSR0_15 F_(D15, IP7_19_16)
PINMUX_IPSR_GPSR(IP7_19_16, D15),
PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
GPIO_FN(D15),
GPIO_FN(D15),
GPIO_FN(D15),
GPIO_FN(D15), GPIO_FN(SCK2_B),
PINMUX_IPSR_GPSR(IP3_1_0, D15),
GPIO_FN(D15),