wed_w32
wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
wed_w32(dev, MTK_WED_TXP_DW1,
wed_w32(dev, MTK_WED_TXP_DW1,
wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8));
wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[0],
wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[1],
wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]);
wed_w32(dev, MTK_WED_RRO_RX_D_CFG(1), dev->wlan.wpdma_rx_rro[1]);
wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING_CFG(i),
wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy);
wed_w32(dev, MTK_WED_WDMA_OFFSET0,
wed_w32(dev, MTK_WED_WDMA_OFFSET1,
wed_w32(dev, MTK_WED_RROQM_MIOD_CFG,
wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL0, dev->rro.miod_phys);
wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL1,
wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL0, dev->rro.fdbk_phys);
wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL1,
wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0);
wed_w32(dev, MTK_WED_RROQ_BASE_L, dev->rro.ring.desc_phys);
wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL2, MTK_WED_MIOD_CNT - 1);
wed_w32(dev, MTK_WED_RESET, MTK_WED_RESET_RX_ROUTE_QM);
wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
wed_w32(dev, MTK_WED_TX_BM_CTRL,
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
wed_w32(dev, MTK_WED_TX_BM_CTRL,
wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
wed_w32(dev, MTK_WED_TX_TKID_CTRL,
wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
wed_w32(dev, MTK_WED_TX_TKID_CTRL,
wed_w32(dev, MTK_WED_TX_BM_INIT_PTR,
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
wed_w32(dev, MTK_WED_RRO_RX_D_CFG(2),
wed_w32(dev, MTK_WED_RESET_IDX, 0);
wed_w32(dev, MTK_WED_RESET_IDX,
wed_w32(dev, MTK_WED_RESET_IDX, 0);
wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
wed_w32(dev, MTK_WED_RX1_CTRL2, 0);
wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_WPDMA_IDX_RX);
wed_w32(dev, MTK_WED_RESET_IDX, 0);
wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_CPU_IDX,
wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_DMA_IDX,
wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE,
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_RX,
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG,
wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_RRO_CFG0, dev->wlan.phy_base +
wed_w32(dev, MTK_WED_RRO_CFG1,
wed_w32(dev, MTK_WED_ADDR_ELEM_CFG0,
wed_w32(dev, MTK_WED_RADDR_ELEM_TBL_WDATA,
wed_w32(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
wed_w32(dev, MTK_WED_PN_CHECK_WDATA_M,
wed_w32(dev, MTK_WED_PN_CHECK_CFG, MTK_WED_PN_CHECK_WR |
wed_w32(dev, MTK_WED_RX_IND_CMD_CNT0, MTK_WED_RX_IND_CMD_DBG_CNT_EN);
wed_w32(dev, addr, 1);
wed_w32(dev, MTK_WED_EXT_INT_MASK1,
wed_w32(dev, MTK_WED_EXT_INT_MASK2,
wed_w32(dev, MTK_WED_EXT_INT_MASK3,
wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
wed_w32(dev, MTK_WED_RING_RX(index) + i, val);
wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val);
wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_BASE,
wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_COUNT,
wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */
wed_w32(dev, MTK_WED_INT_MASK, mask);
.reg_write = wed_w32,
wed_w32(dev, MTK_WED_RESET, mask);
wed_w32(dev, MTK_WED_AMSDU_HIFTXD_BASE_L(i),
wed_w32(dev, MTK_WED_AMSDU_STA_INFO_INIT, MTK_WED_AMSDU_STA_RMVL |
wed_w32(dev, MTK_WED_AMSDU_STA_INFO, MTK_WED_AMSDU_STA_INFO_DO_INIT);
wed_w32(dev, MTK_WED_RRO_PG_BM_BASE, dev->hw_rro.desc_phys);
wed_w32(dev, MTK_WED_RRO_PG_BM_INIT_PTR,
wed_w32(dev, MTK_WED_RX_BM_RX_DMAD,
wed_w32(dev, MTK_WED_RX_BM_BASE, dev->rx_buf_ring.desc_phys);
wed_w32(dev, MTK_WED_RX_BM_INIT_PTR, MTK_WED_RX_BM_INIT_SW_TAIL |
wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH,
wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);
wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,