arch/mips/include/asm/cacheops.h

100

#define Index_Load_Data_D (Cache_D | 0x18)

arch/mips/include/asm/cacheops.h

103

#define Index_Store_Data_D (Cache_D | 0x1c)

arch/mips/include/asm/cacheops.h

38

#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)

arch/mips/include/asm/cacheops.h

40

#define Index_Load_Tag_D (Cache_D | Index_Load_Tag)

arch/mips/include/asm/cacheops.h

42

#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)

arch/mips/include/asm/cacheops.h

44

#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)

arch/mips/include/asm/cacheops.h

45

#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)

arch/mips/include/asm/cacheops.h

50

#define Create_Dirty_Excl_D (Cache_D | 0x0c)

arch/mips/include/asm/cacheops.h

53

#define Hit_Writeback_D (Cache_D | Hit_Writeback)

arch/mips/kvm/vz.c

1108

if (cache != Cache_I && cache != Cache_D)