wave5_vdi_read_register
ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl & FIO_CTRL_READY,
if (wave5_vdi_read_register(vpu_dev, W5_VPU_FIO_DATA) != val)
ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl & FIO_CTRL_READY, 0,
return read_poll_timeout(wave5_vdi_read_register, data, data == 0,
if (wave5_vdi_read_register(vpu_dev, W5_VCPU_CUR_PC) == 0) {
#define vpu_read_reg(CORE, ADDR) wave5_vdi_read_register(CORE, ADDR)
if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) {
if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS))
dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);
irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);
cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST);
wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);
u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr);