wait_info
struct wait_info *winfo = timer_container_of(winfo, t, timer);
static void init_wait_info(struct wait_info *winfo)
static int wait_satisfied(struct wait_info *winfo, struct gpib_status_queue *status_queue,
static void start_wait_timer(struct wait_info *winfo)
static void remove_wait_timer(struct wait_info *winfo)
struct wait_info winfo;
struct drm_amdgpu_userq_wait *wait_info,
for (i = 0; i < wait_info->num_syncobj_timeline_handles; i++) {
for (i = 0; i < wait_info->num_syncobj_handles; i++) {
num_read_bo_handles = wait_info->num_bo_read_handles;
num_write_bo_handles = wait_info->num_bo_write_handles;
wait_info->num_fences = min(num_fences, USHRT_MAX);
amdgpu_userq_wait_add_fence(struct drm_amdgpu_userq_wait *wait_info,
if (*num_fences >= wait_info->num_fences)
struct drm_amdgpu_userq_wait *wait_info,
fence_info = kmalloc_array(wait_info->num_fences, sizeof(*fence_info),
fences = kmalloc_array(wait_info->num_fences, sizeof(*fences),
num_points = wait_info->num_syncobj_timeline_handles;
r = amdgpu_userq_wait_add_fence(wait_info, fences,
num_syncobj = wait_info->num_syncobj_handles;
r = amdgpu_userq_wait_add_fence(wait_info, fences,
num_read_bo_handles = wait_info->num_bo_read_handles;
num_write_bo_handles = wait_info->num_bo_write_handles;
r = amdgpu_userq_wait_add_fence(wait_info, fences,
r = amdgpu_userq_wait_add_fence(wait_info, fences,
waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id);
wait_info->num_fences = cnt;
if (copy_to_user(u64_to_user_ptr(wait_info->out_fences),
struct drm_amdgpu_userq_wait *wait_info = data;
if (wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES ||
wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES)
num_syncobj = wait_info->num_syncobj_handles;
ptr = u64_to_user_ptr(wait_info->syncobj_handles);
num_points = wait_info->num_syncobj_timeline_handles;
ptr = u64_to_user_ptr(wait_info->syncobj_timeline_handles);
ptr = u64_to_user_ptr(wait_info->syncobj_timeline_points);
num_read_bo_handles = wait_info->num_bo_read_handles;
ptr = u64_to_user_ptr(wait_info->bo_read_handles);
num_write_bo_handles = wait_info->num_bo_write_handles;
ptr = u64_to_user_ptr(wait_info->bo_write_handles);
if (!wait_info->num_fences) {
r = amdgpu_userq_wait_count_fences(filp, wait_info,
r = amdgpu_userq_wait_return_fence_info(filp, wait_info,
struct dpu_encoder_wait_info *wait_info)
if (!wait_info) {
atomic_read(wait_info->atomic_cnt));
wait_info);
atomic_read(wait_info->atomic_cnt));
atomic_read(wait_info->atomic_cnt));
atomic_read(wait_info->atomic_cnt));
struct dpu_encoder_wait_info *wait_info);
struct dpu_encoder_wait_info wait_info;
wait_info.wq = &phys_enc->pending_kickoff_wq;
wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
&wait_info);
struct dpu_encoder_wait_info wait_info;
wait_info.wq = &phys_enc->pending_kickoff_wq;
wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
&wait_info);
struct dpu_encoder_wait_info wait_info;
wait_info.wq = &phys_enc->pending_kickoff_wq;
wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
&wait_info);
struct dpu_encoder_wait_info wait_info;
wait_info.wq = &phys_enc->pending_kickoff_wq;
wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
dpu_encoder_phys_wb_done_irq, &wait_info);