drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

126

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

134

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

142

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

150

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

28

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

36

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

44

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

53

struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

54

struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

71

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

79

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

87

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

97

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/display/xe_initial_plane.c

32

struct xe_reg pipe_frmtmstmp = XE_REG(i915_mmio_reg_offset(PIPE_FRMTMSTMP(crtc->pipe)));

drivers/gpu/drm/xe/regs/xe_reg_defs.h

120

#define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))

drivers/gpu/drm/xe/regs/xe_reg_defs.h

132

static inline bool xe_reg_is_valid(struct xe_reg r)

drivers/gpu/drm/xe/regs/xe_reg_defs.h

61

static_assert(sizeof(struct xe_reg) == sizeof(u32));

drivers/gpu/drm/xe/regs/xe_reg_defs.h

72

struct xe_reg __reg;

drivers/gpu/drm/xe/tests/xe_rtp_test.c

36

struct xe_reg expected_reg;

drivers/gpu/drm/xe/xe_force_wake.c

32

struct xe_reg reg, struct xe_reg ack)

drivers/gpu/drm/xe/xe_force_wake_types.h

76

struct xe_reg reg_ctl;

drivers/gpu/drm/xe/xe_force_wake_types.h

78

struct xe_reg reg_ack;

drivers/gpu/drm/xe/xe_gt.c

285

struct xe_reg reg = entry->reg;

drivers/gpu/drm/xe/xe_gt_mcr.c

48

static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)

drivers/gpu/drm/xe/xe_gt_mcr.c

632

const struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.c

713

const struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.c

715

struct xe_reg steer_reg;

drivers/gpu/drm/xe/xe_gt_mcr.c

780

const struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_mcr.c

859

struct xe_reg reg = to_xe_reg(reg_mcr);

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

101

static const struct xe_reg ver_35_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

117

static const struct xe_reg *pick_runtime_regs(struct xe_device *xe, unsigned int *count)

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

119

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

153

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

181

const struct xe_reg *regs, u32 *values)

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

189

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

23

static const struct xe_reg tgl_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

33

static const struct xe_reg ats_m_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

408

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

44

static const struct xe_reg pvc_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

55

static const struct xe_reg ver_1270_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

68

static const struct xe_reg ver_2000_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

84

static const struct xe_reg ver_3000_runtime_regs[] = {

drivers/gpu/drm/xe/xe_gt_sriov_pf_service_types.h

11

struct xe_reg;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service_types.h

32

const struct xe_reg *regs;

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1079

u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg)

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1114

void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)

drivers/gpu/drm/xe/xe_gt_sriov_vf.h

13

struct xe_reg;

drivers/gpu/drm/xe/xe_gt_sriov_vf.h

35

u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg);

drivers/gpu/drm/xe/xe_gt_sriov_vf.h

36

void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);

drivers/gpu/drm/xe/xe_gt_throttle.c

87

struct xe_reg reg;

drivers/gpu/drm/xe/xe_gt_topology.c

21

const struct xe_reg regs[])

drivers/gpu/drm/xe/xe_gt_topology.c

229

static const struct xe_reg geometry_regs[] = {

drivers/gpu/drm/xe/xe_gt_topology.c

234

static const struct xe_reg compute_regs[] = {

drivers/gpu/drm/xe/xe_guc.c

1420

struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?

drivers/gpu/drm/xe/xe_guc_ads.c

706

struct xe_reg reg,

drivers/gpu/drm/xe/xe_guc_ads.c

742

struct xe_reg reg;

drivers/gpu/drm/xe/xe_guc_capture_types.h

31

struct xe_reg reg;

drivers/gpu/drm/xe/xe_guc_types.h

124

struct xe_reg notify_reg;

drivers/gpu/drm/xe/xe_huc.c

220

struct xe_reg reg;

drivers/gpu/drm/xe/xe_hw_engine.c

296

struct xe_reg reg, u32 val)

drivers/gpu/drm/xe/xe_hw_engine.c

316

u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)

drivers/gpu/drm/xe/xe_hw_engine.h

79

void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);

drivers/gpu/drm/xe/xe_hw_engine.h

80

u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);

drivers/gpu/drm/xe/xe_hwmon.c

1072

struct xe_reg reg;

drivers/gpu/drm/xe/xe_hwmon.c

1466

struct xe_reg pkg_power_sku_unit;

drivers/gpu/drm/xe/xe_hwmon.c

255

static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,

drivers/gpu/drm/xe/xe_hwmon.c

333

struct xe_reg rapl_limit, pkg_power_sku;

drivers/gpu/drm/xe/xe_hwmon.c

378

struct xe_reg rapl_limit;

drivers/gpu/drm/xe/xe_hwmon.c

463

struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);

drivers/gpu/drm/xe/xe_hwmon.c

696

struct xe_reg rapl_limit;

drivers/gpu/drm/xe/xe_hwmon.c

922

struct xe_reg vram_reg;

drivers/gpu/drm/xe/xe_irq.c

42

static void assert_iir_is_zero(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

144

u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

157

u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

170

void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val)

drivers/gpu/drm/xe/xe_mmio.c

183

u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

201

u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set)

drivers/gpu/drm/xe/xe_mmio.c

213

struct xe_reg reg, u32 val, u32 mask, u32 eval)

drivers/gpu/drm/xe/xe_mmio.c

225

struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

254

u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)

drivers/gpu/drm/xe/xe_mmio.c

256

struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };

drivers/gpu/drm/xe/xe_mmio.c

282

static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,

drivers/gpu/drm/xe/xe_mmio.c

354

int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,

drivers/gpu/drm/xe/xe_mmio.c

373

int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,

drivers/gpu/drm/xe/xe_mmio.h

12

struct xe_reg;

drivers/gpu/drm/xe/xe_mmio.h

19

u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

20

u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

21

void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);

drivers/gpu/drm/xe/xe_mmio.h

22

u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

23

u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);

drivers/gpu/drm/xe/xe_mmio.h

24

int xe_mmio_write32_and_verify(struct xe_mmio *mmio, struct xe_reg reg, u32 val, u32 mask, u32 eval);

drivers/gpu/drm/xe/xe_mmio.h

25

bool xe_mmio_in_range(const struct xe_mmio *mmio, const struct xe_mmio_range *range, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

27

u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg);

drivers/gpu/drm/xe/xe_mmio.h

28

int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,

drivers/gpu/drm/xe/xe_mmio.h

30

int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,

drivers/gpu/drm/xe/xe_nvm.c

62

struct xe_reg reg;

drivers/gpu/drm/xe/xe_oa.c

2137

static const struct xe_reg flex_eu_regs[] = {

drivers/gpu/drm/xe/xe_oa.c

392

struct xe_reg oaheadptr = __oa_regs(stream)->oa_head_ptr;

drivers/gpu/drm/xe/xe_oa.c

64

struct xe_reg addr;

drivers/gpu/drm/xe/xe_oa_types.h

83

struct xe_reg oa_head_ptr;

drivers/gpu/drm/xe/xe_oa_types.h

84

struct xe_reg oa_tail_ptr;

drivers/gpu/drm/xe/xe_oa_types.h

85

struct xe_reg oa_buffer;

drivers/gpu/drm/xe/xe_oa_types.h

86

struct xe_reg oa_ctx_ctrl;

drivers/gpu/drm/xe/xe_oa_types.h

87

struct xe_reg oa_ctrl;

drivers/gpu/drm/xe/xe_oa_types.h

88

struct xe_reg oa_debug;

drivers/gpu/drm/xe/xe_oa_types.h

89

struct xe_reg oa_status;

drivers/gpu/drm/xe/xe_oa_types.h

90

struct xe_reg oa_mmio_trg;

drivers/gpu/drm/xe/xe_pat.c

280

struct xe_reg reg = XE_REG(_PAT_INDEX(i));

drivers/gpu/drm/xe/xe_pci.c

537

struct xe_reg gmdid_reg = GMD_ID;

drivers/gpu/drm/xe/xe_query.c

98

struct xe_reg upper_reg = RING_TIMESTAMP_UDW(hwe->mmio_base),

drivers/gpu/drm/xe/xe_reg_sr.c

123

static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg)

drivers/gpu/drm/xe/xe_reg_sr.c

130

struct xe_reg reg = entry->reg;

drivers/gpu/drm/xe/xe_reg_sr_types.h

15

struct xe_reg reg;

drivers/gpu/drm/xe/xe_ring_ops.c

51

static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,

drivers/gpu/drm/xe/xe_rtp_types.h

25

struct xe_reg reg;

drivers/gpu/drm/xe/xe_soc_remapper.c

10

static void xe_soc_remapper_set_region(struct xe_device *xe, struct xe_reg reg,