drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

108

return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,

drivers/gpu/drm/xe/xe_device.c

1109

if (xe_mmio_wait32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,

drivers/gpu/drm/xe/xe_device.c

1133

if (xe_mmio_wait32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 1000, NULL, true))

drivers/gpu/drm/xe/xe_device.c

578

ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);

drivers/gpu/drm/xe/xe_device.c

589

ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);

drivers/gpu/drm/xe/xe_device.c

596

ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS,

drivers/gpu/drm/xe/xe_force_wake.c

112

ret = xe_mmio_wait32(&gt->mmio, domain->reg_ack, domain->val, wake ? domain->val : 0,

drivers/gpu/drm/xe/xe_gsc.c

196

return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE),

drivers/gpu/drm/xe/xe_gsc_proxy.c

80

return xe_mmio_wait32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE),

drivers/gpu/drm/xe/xe_gt.c

778

err = xe_mmio_wait32(&gt->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false);

drivers/gpu/drm/xe/xe_gt_mcr.c

690

ret = xe_mmio_wait32(&gt->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,

drivers/gpu/drm/xe/xe_guc.c

1453

ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN,

drivers/gpu/drm/xe/xe_guc.c

1485

ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask,

drivers/gpu/drm/xe/xe_guc.c

917

ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);

drivers/gpu/drm/xe/xe_huc.c

274

ret = xe_mmio_wait32(&gt->mmio, huc_auth_modes[type].reg, huc_auth_modes[type].val,

drivers/gpu/drm/xe/xe_mmio.h

28

int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,

drivers/gpu/drm/xe/xe_oa.c

496

if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl,

drivers/gpu/drm/xe/xe_oa.c

504

if (xe_mmio_wait32(mmio, OA_TLB_INV_CR, 1, 0, 50000, NULL, false))

drivers/gpu/drm/xe/xe_pcode.c

87

err = xe_mmio_wait32(mmio, PCODE_MAILBOX, PCODE_READY, 0,

drivers/gpu/drm/xe/xe_pxp.c

124

return xe_mmio_wait32(&gt->mmio, KCR_SIP, mask, in_play ? mask : 0,

drivers/gpu/drm/xe/xe_uc_fw.c

887

ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,