drivers/gpu/drm/xe/tests/xe_mocs.c

56

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i >> 1));

drivers/gpu/drm/xe/tests/xe_mocs.c

93

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_device.c

775

reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);

drivers/gpu/drm/xe/xe_gt.c

114

reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);

drivers/gpu/drm/xe/xe_gt.c

136

reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);

drivers/gpu/drm/xe/xe_gt.c

155

reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);

drivers/gpu/drm/xe/xe_gt.c

162

reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMWALK_CTRL_3D);

drivers/gpu/drm/xe/xe_gt_mcr.h

22

u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr mcr_reg);

drivers/gpu/drm/xe/xe_mocs.c

277

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

309

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

382

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

427

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

509

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_mocs.c

552

reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

drivers/gpu/drm/xe/xe_pat.c

345

u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

370

u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

400

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

458

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

471

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));

drivers/gpu/drm/xe/xe_pat.c

499

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));

drivers/gpu/drm/xe/xe_pat.c

509

pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));

drivers/gpu/drm/xe/xe_reg_sr.c

146

xe_gt_mcr_unicast_read_any(gt, reg_mcr) :

drivers/gpu/drm/xe/xe_vram.c

82

reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);

drivers/gpu/drm/xe/xe_vram.c

85

reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_UPPER);

drivers/gpu/drm/xe/xe_vram.c

98

reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);