vpu_write_reg
vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr);
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size);
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN);
vpu_write_reg(vpu_dev, W5_PO_CONF, 0);
vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);
vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);
vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0);
vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base);
vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size);
vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF,
vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE,
vpu_write_reg(vpu_dev,
vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI,
vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE,
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU);
vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU);
vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1);
vpu_write_reg(vpu_dev, W5_PO_CONF, 0);
vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);
vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);
vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0);
vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF,
vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE,
vpu_write_reg(vpu_dev,
vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI,
vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE,
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU);
vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0);
vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, val);
vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0);
vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0);
vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));
vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr);
vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index));
vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0);
vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0);
vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index));
vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason);
vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr);
vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr);
vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size);
vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val);
vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, WAVE521_COMMAND_QUEUE_DEPTH - 1);
vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i |
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p |
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT,
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0);
vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF,
vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size);
vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr);
vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size);
vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size);
vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride);
vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride);
vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val);
vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no);
vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i +
vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4),
vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4),
vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4),
vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2),
vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr);
vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION,
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION,
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE,
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format |
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0);
vpu_write_reg(vpu_dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) |
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0);
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
vpu_write_reg(vpu_dev, W5_COMMAND, cmd);
vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1);
vpu_write_reg(vpu_dev, W5_QUERY_OPTION, query_opt);
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, REMAP_CTRL_REGISTER_VALUE(index));
vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE);
vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE);
vpu_write_reg(vpu_dev, W5_PO_CONF, 0);
vpu_write_reg(vpu_dev, i, 0x00);
vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);
vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);
vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0);
vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base);
vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size);
vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, WAVE515_COMMAND_QUEUE_DEPTH);
vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, WAVE515_ONE_TASKBUF_SIZE);
vpu_write_reg(vpu_dev,
vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);
vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU);
vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);
vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1);
vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr);
vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size);
vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr);
vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size);
vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr);
vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size);
vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN);
vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1,
vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, 0);
vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr);
vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr);
vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option);
vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option);
vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable);
vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr);
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size);
vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN);
vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF,
vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE,
vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size);
vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val);
vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val);
vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no);
vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y);
vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb);
vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4),
vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4),
vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2),
vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr);
vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0);
vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0);
vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr);
vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr);
vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));
vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val);
vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable);
vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL);
vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1,
vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask);
vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable);