vpll
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
[vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
[vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
[vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p,
[vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
exynos4210_plls[vpll].rate_table =
exynos4x12_plls[vpll].rate_table =
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
[vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
[vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
[vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
struct dss_video_pll *vpll;
vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
if (!vpll)
vpll->dev = &pdev->dev;
vpll->clkctrl_base = clkctrl_base;
pll = &vpll->pll;
static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
static void dss_dpll_power_enable(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
static void dss_dpll_power_disable(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
dss_dpll_enable_scp_clk(vpll);
dss_dpll_power_enable(vpll);
dss_dpll_disable_scp_clk(vpll);
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
dss_dpll_power_disable(vpll);
dss_dpll_disable_scp_clk(vpll);
vpll = (ret >> 4) & 1; /* Save bit 4 */
vpll |= (ret >> 1) & 2;
vpll_val[vpll] / 100, vpll_val[vpll] % 100,
u8 vpll;
MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
u32 vpll;
state->vpll = state->pll;
state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
struct dss_video_pll *vpll;
vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
if (!vpll)
vpll->dev = &pdev->dev;
vpll->clkctrl_base = clkctrl_base;
pll = &vpll->pll;
static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
static void dss_dpll_power_enable(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
static void dss_dpll_power_disable(struct dss_video_pll *vpll)
REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
dss_dpll_enable_scp_clk(vpll);
dss_dpll_power_enable(vpll);
dss_dpll_disable_scp_clk(vpll);
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
dss_dpll_power_disable(vpll);
dss_dpll_disable_scp_clk(vpll);
newmode.ext.vpll2 = newmode.ext.vpll;
state->vpll = (p << 16) | (n << 8) | m;
NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
U032 vpll;