arch/arm64/kvm/vgic/vgic-its.c

337

if (map.vpe)

arch/arm64/kvm/vgic/vgic-its.c

338

atomic_dec(&map.vpe->vlpi_count);

arch/arm64/kvm/vgic/vgic-its.c

340

map.vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;

arch/arm64/kvm/vgic/vgic-its.c

341

atomic_inc(&map.vpe->vlpi_count);

arch/arm64/kvm/vgic/vgic-v4.c

108

static void vgic_v4_sync_sgi_config(struct its_vpe *vpe, struct vgic_irq *irq)

arch/arm64/kvm/vgic/vgic-v4.c

110

vpe->sgi_config[irq->intid].enabled = irq->enabled;

arch/arm64/kvm/vgic/vgic-v4.c

111

vpe->sgi_config[irq->intid].group = irq->group;

arch/arm64/kvm/vgic/vgic-v4.c

112

vpe->sgi_config[irq->intid].priority = irq->priority;

arch/arm64/kvm/vgic/vgic-v4.c

117

struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;

arch/arm64/kvm/vgic/vgic-v4.c

137

irq->host_irq = irq_find_mapping(vpe->sgi_domain, i);

arch/arm64/kvm/vgic/vgic-v4.c

140

vgic_v4_sync_sgi_config(vpe, irq);

arch/arm64/kvm/vgic/vgic-v4.c

218

struct its_vpe *vpe = &irq->target_vcpu->arch.vgic_cpu.vgic_v3.its_vpe;

arch/arm64/kvm/vgic/vgic-v4.c

223

va = page_address(vpe->vpt_page);

arch/arm64/kvm/vgic/vgic-v4.c

360

struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;

arch/arm64/kvm/vgic/vgic-v4.c

362

if (!vgic_supports_direct_irqs(vcpu->kvm) || !vpe->resident)

arch/arm64/kvm/vgic/vgic-v4.c

365

return its_make_vpe_non_resident(vpe, vgic_v4_want_doorbell(vcpu));

arch/arm64/kvm/vgic/vgic-v4.c

370

struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;

arch/arm64/kvm/vgic/vgic-v4.c

373

if (!vgic_supports_direct_irqs(vcpu->kvm) || vpe->resident)

arch/arm64/kvm/vgic/vgic-v4.c

385

err = irq_set_affinity(vpe->irq, cpumask_of(smp_processor_id()));

arch/arm64/kvm/vgic/vgic-v4.c

389

err = its_make_vpe_resident(vpe, false, vcpu->kvm->arch.vgic.enabled);

arch/arm64/kvm/vgic/vgic-v4.c

399

err = irq_set_irqchip_state(vpe->irq, IRQCHIP_STATE_PENDING, false);

arch/arm64/kvm/vgic/vgic-v4.c

406

struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;

arch/arm64/kvm/vgic/vgic-v4.c

412

if (!vpe->ready)

arch/arm64/kvm/vgic/vgic-v4.c

413

its_commit_vpe(vpe);

arch/arm64/kvm/vgic/vgic-v4.c

477

.vpe = &irq->target_vcpu->arch.vgic_cpu.vgic_v3.its_vpe,

arch/arm64/kvm/vgic/vgic-v4.c

491

atomic_inc(&map.vpe->vlpi_count);

arch/mips/include/asm/cpu-info.h

178

extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);

arch/mips/include/asm/rtlx.h

30

void rtlx_starting(int vpe);

arch/mips/include/asm/rtlx.h

31

void rtlx_stopping(int vpe);

arch/mips/include/asm/smp-cps.h

36

extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);

arch/mips/include/asm/vpe.h

108

struct vpe *get_vpe(int minor);

arch/mips/include/asm/vpe.h

110

struct vpe *alloc_vpe(int minor);

arch/mips/include/asm/vpe.h

112

void release_vpe(struct vpe *v);

arch/mips/include/asm/vpe.h

117

int vpe_run(struct vpe *v);

arch/mips/include/asm/vpe.h

125

int vpe_start(void *vpe, unsigned long start);

arch/mips/include/asm/vpe.h

126

int vpe_stop(void *vpe);

arch/mips/include/asm/vpe.h

127

int vpe_free(void *vpe);

arch/mips/include/asm/vpe.h

82

struct vpe *pvpe; /* parent VPE */

arch/mips/include/asm/vpe.h

88

void (*start)(int vpe);

arch/mips/include/asm/vpe.h

89

void (*stop)(int vpe);

arch/mips/kernel/cpu-probe.c

2042

void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)

arch/mips/kernel/cpu-probe.c

2045

WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));

arch/mips/kernel/cpu-probe.c

2048

WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&

arch/mips/kernel/cpu-probe.c

2052

cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;

arch/mips/kernel/perf_event_mipsxx.c

98

#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)

arch/mips/kernel/rtlx.c

68

void rtlx_starting(int vpe)

arch/mips/kernel/rtlx.c

81

void rtlx_stopping(int vpe)

arch/mips/kernel/vpe-mt.c

180

struct vpe *v;

arch/mips/kernel/vpe-mt.c

195

int vpe_start(void *vpe, unsigned long start)

arch/mips/kernel/vpe-mt.c

197

struct vpe *v = vpe;

arch/mips/kernel/vpe-mt.c

205

int vpe_stop(void *vpe)

arch/mips/kernel/vpe-mt.c

207

struct vpe *v = vpe;

arch/mips/kernel/vpe-mt.c

226

int vpe_free(void *vpe)

arch/mips/kernel/vpe-mt.c

228

struct vpe *v = vpe;

arch/mips/kernel/vpe-mt.c

26

int vpe_run(struct vpe *v)

arch/mips/kernel/vpe-mt.c

263

struct vpe *vpe = get_vpe(aprp_cpu_index());

arch/mips/kernel/vpe-mt.c

266

list_for_each_entry(notifier, &vpe->notify, list)

arch/mips/kernel/vpe-mt.c

269

release_progmem(vpe->load_addr);

arch/mips/kernel/vpe-mt.c

271

vpe_stop(vpe);

arch/mips/kernel/vpe-mt.c

272

vpe_free(vpe);

arch/mips/kernel/vpe-mt.c

281

struct vpe *vpe = get_vpe(aprp_cpu_index());

arch/mips/kernel/vpe-mt.c

283

return sprintf(buf, "%d\n", vpe->ntcs);

arch/mips/kernel/vpe-mt.c

289

struct vpe *vpe = get_vpe(aprp_cpu_index());

arch/mips/kernel/vpe-mt.c

300

vpe->ntcs = new;

arch/mips/kernel/vpe-mt.c

311

ATTRIBUTE_GROUPS(vpe);

arch/mips/kernel/vpe-mt.c

329

struct vpe *v = NULL;

arch/mips/kernel/vpe-mt.c

508

struct vpe *v, *n;

arch/mips/kernel/vpe.c

134

void release_vpe(struct vpe *v)

arch/mips/kernel/vpe.c

54

struct vpe *get_vpe(int minor)

arch/mips/kernel/vpe.c

550

static int find_vpe_symbols(struct vpe *v, Elf_Shdr *sechdrs,

arch/mips/kernel/vpe.c

56

struct vpe *res, *v;

arch/mips/kernel/vpe.c

576

static int vpe_elfload(struct vpe *v)

arch/mips/kernel/vpe.c

754

struct vpe *v;

arch/mips/kernel/vpe.c

799

struct vpe *v;

arch/mips/kernel/vpe.c

842

struct vpe *v;

arch/mips/kernel/vpe.c

875

struct vpe *v = get_vpe(index);

arch/mips/kernel/vpe.c

886

struct vpe *v = get_vpe(index);

arch/mips/kernel/vpe.c

93

struct vpe *alloc_vpe(int minor)

arch/mips/kernel/vpe.c

95

struct vpe *v;

arch/mips/kernel/vpe.c

97

v = kzalloc_obj(struct vpe);

arch/mips/lantiq/irq.c

102

int vpe;

arch/mips/lantiq/irq.c

107

for_each_present_cpu(vpe) {

arch/mips/lantiq/irq.c

108

ltq_icu_w32(vpe, im,

arch/mips/lantiq/irq.c

109

ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),

arch/mips/lantiq/irq.c

111

ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);

arch/mips/lantiq/irq.c

121

int vpe;

arch/mips/lantiq/irq.c

126

for_each_present_cpu(vpe) {

arch/mips/lantiq/irq.c

127

ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);

arch/mips/lantiq/irq.c

137

int vpe;

arch/mips/lantiq/irq.c

141

vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));

arch/mips/lantiq/irq.c

144

if (unlikely(vpe >= nr_cpu_ids))

arch/mips/lantiq/irq.c

145

vpe = smp_processor_id();

arch/mips/lantiq/irq.c

149

ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),

arch/mips/lantiq/irq.c

292

int vpe = smp_processor_id();

arch/mips/lantiq/irq.c

294

irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);

arch/mips/lantiq/irq.c

344

int i, ret, vpe;

arch/mips/lantiq/irq.c

347

for_each_possible_cpu(vpe) {

arch/mips/lantiq/irq.c

348

if (of_address_to_resource(node, vpe, &res))

arch/mips/lantiq/irq.c

349

panic("Failed to get icu%i memory range", vpe);

arch/mips/lantiq/irq.c

353

pr_err("Failed to request icu%i memory\n", vpe);

arch/mips/lantiq/irq.c

355

ltq_icu_membase[vpe] = ioremap(res.start,

arch/mips/lantiq/irq.c

358

if (!ltq_icu_membase[vpe])

arch/mips/lantiq/irq.c

359

panic("Failed to remap icu%i memory", vpe);

arch/mips/lantiq/irq.c

363

for_each_possible_cpu(vpe) {

arch/mips/lantiq/irq.c

366

ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);

arch/mips/lantiq/irq.c

369

ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);

arch/mips/lantiq/irq.c

370

ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);

arch/mips/lantiq/irq.c

373

ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);

arch/mips/lantiq/irq.c

51

#define ltq_icu_w32(vpe, m, x, y) \

arch/mips/lantiq/irq.c

52

ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))

arch/mips/lantiq/irq.c

54

#define ltq_icu_r32(vpe, m, x) \

arch/mips/lantiq/irq.c

55

ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))

arch/mips/lantiq/irq.c

84

int vpe;

arch/mips/lantiq/irq.c

89

for_each_present_cpu(vpe) {

arch/mips/lantiq/irq.c

90

ltq_icu_w32(vpe, im,

arch/mips/lantiq/irq.c

91

ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),

drivers/gpu/drm/amd/amdgpu/amdgpu.h

975

struct amdgpu_vpe vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c

197

adev->vpe.feature_version, adev->vpe.fw_version);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1595

if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1596

adev->vpe.num_instances++;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1599

adev->vpe.num_instances + 1,

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

368

fw_info->ver = adev->vpe.fw_version;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

369

fw_info->feature = adev->vpe.feature_version;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

574

if (adev->vpe.ring.sched.ready &&

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

575

!adev->vpe.ring.no_user_submission)

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

764

count = adev->vpe.num_instances;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

1006

adev->vpe.ring.funcs = &vpe_ring_funcs;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

122

int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

124

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

136

dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

138

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

200

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

201

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

202

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

203

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

204

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

214

dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

216

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

225

.mc_addr = adev->vpe.cmdbuf_gpu_addr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

232

int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

234

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

240

ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

245

vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

246

adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

247

adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

254

info->fw = adev->vpe.fw;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

260

info->fw = adev->vpe.fw;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

268

release_firmware(adev->vpe.fw);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

269

adev->vpe.fw = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

273

int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

275

struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

276

struct amdgpu_ring *ring = &vpe->ring;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

285

ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

293

int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

295

amdgpu_ring_fini(&vpe->ring);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

303

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

308

vpe_v6_1_set_funcs(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

311

vpe_v6_1_set_funcs(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

312

vpe->collaborate_mode = true;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

316

vpe_v2_0_set_funcs(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

323

vpe_set_regs(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

325

dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false");

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

342

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

347

return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

353

container_of(work, struct amdgpu_device, vpe.idle_work.work);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

356

fences += amdgpu_fence_count_emitted(&adev->vpe.ring);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

367

schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

370

static int vpe_common_init(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

372

struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

377

&adev->vpe.cmdbuf_obj,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

378

&adev->vpe.cmdbuf_gpu_addr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

379

(void **)&adev->vpe.cmdbuf_cpu_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

385

vpe->context_started = false;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

386

INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

394

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

397

ret = vpe_common_init(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

401

ret = vpe_irq_init(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

405

ret = vpe_ring_init(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

409

ret = vpe_init_microcode(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

413

adev->vpe.supported_reset =

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

414

amdgpu_get_soft_full_reset_mask(&adev->vpe.ring);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

416

adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

427

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

429

release_firmware(vpe->fw);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

430

vpe->fw = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

433

vpe_ring_fini(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

435

amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

436

&adev->vpe.cmdbuf_gpu_addr,

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

437

(void **)&adev->vpe.cmdbuf_cpu_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

445

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

454

ret = vpe_load_microcode(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

458

ret = vpe_ring_start(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

468

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

470

cancel_delayed_work_sync(&adev->vpe.idle_work);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

472

vpe_ring_stop(vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

521

if (!ring->adev->vpe.collaborate_mode)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

571

if (ring->adev->vpe.collaborate_mode) {

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

647

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

648

uint32_t preempt_reg = vpe->regs.queue0_preempt;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

661

WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

677

WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

695

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

704

vpe->context_started = false;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

715

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

722

rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

724

rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

734

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

741

wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

743

wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

753

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

765

if (vpe->collaborate_mode)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

770

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

776

WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

778

WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

883

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

885

cancel_delayed_work_sync(&adev->vpe.idle_work);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

888

if (!vpe->context_started) {

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

895

context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

900

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

901

vpe->context_started = true;

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

909

schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

943

return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

953

if (adev->vpe.num_instances) {

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

965

if (adev->vpe.num_instances)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

100

#define vpe_set_regs(vpe) \

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

101

((vpe)->funcs->set_regs ? (vpe)->funcs->set_regs((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

102

#define vpe_irq_init(vpe) \

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

103

((vpe)->funcs->irq_init ? (vpe)->funcs->irq_init((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

104

#define vpe_init_microcode(vpe) \

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

105

((vpe)->funcs->init_microcode ? (vpe)->funcs->init_microcode((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

106

#define vpe_load_microcode(vpe) \

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

107

((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

35

uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

36

int (*set_regs)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

37

int (*irq_init)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

38

int (*init_microcode)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

39

int (*load_microcode)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

40

int (*ring_init)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

41

int (*ring_start)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

42

int (*ring_stop)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

43

int (*ring_fini)(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

86

int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

87

int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

88

int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

89

int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

93

#define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ? (vpe)->funcs->ring_init((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

94

#define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ? (vpe)->funcs->ring_start((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

95

#define vpe_ring_stop(vpe) ((vpe)->funcs->ring_stop ? (vpe)->funcs->ring_stop((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

96

#define vpe_ring_fini(vpe) ((vpe)->funcs->ring_fini ? (vpe)->funcs->ring_fini((vpe)) : 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

98

#define vpe_get_reg_offset(vpe, inst, offset) \

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h

99

((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

282

adev->vpe.collaborate_mode ? 0x3 : 0x0;

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

358

add_queue.collaboration_mode = adev->vpe.collaborate_mode ? 1 : 0;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

100

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

110

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

112

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_CHECKSUM));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

117

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE1_CHECKSUM));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

123

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS2));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

129

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS6));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

136

vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

145

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

147

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

149

for (int j = 0; j < vpe->num_instances; j++) {

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

152

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

154

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

156

data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

162

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

167

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

169

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

175

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

180

static int vpe_v2_0_ring_start(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

182

struct amdgpu_ring *ring = &vpe->ring;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

189

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

192

rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

196

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

199

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

200

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

201

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

202

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

205

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

207

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

212

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

213

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

218

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

219

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

220

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

222

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

224

doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

226

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

228

doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

230

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

236

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

238

ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

240

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

250

static int vpe_v2_0_ring_stop(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

252

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

256

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

257

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

261

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

270

vpe->ring.sched.ready = false;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

280

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

283

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

287

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

301

amdgpu_fence_process(&adev->vpe.ring);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

310

static int vpe_v2_0_set_regs(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

312

vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

313

vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

314

vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

315

vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

316

vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

317

vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

319

vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

320

vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

321

vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

322

vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

323

vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

324

vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

325

vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

347

void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

349

vpe->funcs = &vpe_v2_0_funcs;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

350

vpe->trap_irq.funcs = &vpe_v2_0_trap_irq_funcs;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

38

static uint32_t vpe_v2_0_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

42

base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

47

static int vpe_v2_0_irq_init(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

49

struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

54

&adev->vpe.trap_irq);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

61

static int vpe_v2_0_load_microcode(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

63

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

69

ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

71

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

73

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

75

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2), reg_data);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

77

if (amdgpu_vpe_configure_dpm(vpe))

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

82

f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

87

adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

88

adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

94

f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h

27

void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

100

static void vpe_v6_1_set_collaborate_mode(struct amdgpu_vpe *vpe, bool enable)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

102

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

105

if (!vpe->collaborate_mode)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

108

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

109

vpe_colla_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

112

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL), vpe_colla_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

114

vpe_colla_cfg = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

119

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG), vpe_colla_cfg);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

123

static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

125

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

133

for (j = 0; j < vpe->num_instances; j++) {

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

136

ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

138

ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

143

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1), ret);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

145

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

149

vpe_v6_1_set_collaborate_mode(vpe, true);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

151

if (amdgpu_vpe_configure_dpm(vpe))

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

161

f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

166

adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

167

adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

172

vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

181

vpe_v6_1_halt(vpe, true);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

183

for (j = 0; j < vpe->num_instances; j++) {

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

186

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

188

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

190

data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

196

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

201

vpe_v6_1_halt(vpe, false);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

206

static int vpe_v6_1_ring_start(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

208

struct amdgpu_ring *ring = &vpe->ring;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

215

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

218

rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

222

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

225

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

226

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

227

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

228

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

231

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

233

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

238

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

239

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

244

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

245

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

246

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

248

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

250

doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

252

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

254

doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

256

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

262

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

264

ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

266

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

276

static int vpe_v_6_1_ring_stop(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

278

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

282

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

284

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

286

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

291

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1), queue_reset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

295

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

304

vpe->ring.sched.ready = false;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

314

struct amdgpu_vpe *vpe = &adev->vpe;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

318

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

320

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

326

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1), vpe_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

328

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

342

amdgpu_fence_process(&adev->vpe.ring);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

351

static int vpe_v6_1_set_regs(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

353

struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

355

vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

356

vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

357

vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

358

vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

359

vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

362

vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2_6_1_1;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

364

vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

366

vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

367

vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

368

vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

369

vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

370

vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

371

vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

372

vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

394

void vpe_v6_1_set_funcs(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

396

vpe->funcs = &vpe_v6_1_funcs;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

397

vpe->trap_irq.funcs = &vpe_v6_1_trap_irq_funcs;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

64

static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

68

base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

73

static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

75

struct amdgpu_device *adev = vpe->ring.adev;

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

78

for (i = 0; i < vpe->num_instances; i++) {

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

79

f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

82

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

86

static int vpe_v6_1_irq_init(struct amdgpu_vpe *vpe)

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

88

struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

93

&adev->vpe.trap_irq);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.h

27

void vpe_v6_1_set_funcs(struct amdgpu_vpe *vpe);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

285

unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

287

vpe = mode->crtc_vsync_end - mode->crtc_vsync_start;

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

299

vpe << JZ_LCD_VSYNC_VPE_OFFSET);

drivers/gpu/drm/ingenic/ingenic-drm-drv.c

333

(ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB);

drivers/irqchip/irq-gic-v3-its.c

1002

return valid_vpe(its, desc->its_vmovp_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

1020

return valid_vpe(its, map->vpe);

drivers/irqchip/irq-gic-v3-its.c

1038

return valid_vpe(its, map->vpe);

drivers/irqchip/irq-gic-v3-its.c

1056

return valid_vpe(its, map->vpe);

drivers/irqchip/irq-gic-v3-its.c

1067

its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

1071

return valid_vpe(its, desc->its_invdb_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

1082

its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

1091

return valid_vpe(its, desc->its_vsgi_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

1374

desc.its_vmapti_cmd.vpe = map->vpe;

drivers/irqchip/irq-gic-v3-its.c

1388

desc.its_vmovi_cmd.vpe = map->vpe;

drivers/irqchip/irq-gic-v3-its.c

1397

struct its_vpe *vpe, bool valid)

drivers/irqchip/irq-gic-v3-its.c

1401

desc.its_vmapp_cmd.vpe = vpe;

drivers/irqchip/irq-gic-v3-its.c

1403

desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];

drivers/irqchip/irq-gic-v3-its.c

1408

static void its_send_vmovp(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

1412

int col_id = vpe->col_idx;

drivers/irqchip/irq-gic-v3-its.c

1414

desc.its_vmovp_cmd.vpe = vpe;

drivers/irqchip/irq-gic-v3-its.c

1433

desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);

drivers/irqchip/irq-gic-v3-its.c

1440

if (!require_its_list_vmovp(vpe->its_vm, its))

drivers/irqchip/irq-gic-v3-its.c

1448

static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

1452

desc.its_vinvall_cmd.vpe = vpe;

drivers/irqchip/irq-gic-v3-its.c

1498

static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

1502

desc.its_invdb_cmd.vpe = vpe;

drivers/irqchip/irq-gic-v3-its.c

1578

val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

1890

struct its_vpe *vpe = vm->vpes[i];

drivers/irqchip/irq-gic-v3-its.c

1892

scoped_guard(raw_spinlock, &vpe->vpe_lock)

drivers/irqchip/irq-gic-v3-its.c

1893

its_send_vmapp(its, vpe, true);

drivers/irqchip/irq-gic-v3-its.c

1895

its_send_vinvall(its, vpe);

drivers/irqchip/irq-gic-v3-its.c

359

static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)

drivers/irqchip/irq-gic-v3-its.c

361

raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);

drivers/irqchip/irq-gic-v3-its.c

362

return vpe->col_idx;

drivers/irqchip/irq-gic-v3-its.c

365

static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)

drivers/irqchip/irq-gic-v3-its.c

367

raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);

drivers/irqchip/irq-gic-v3-its.c

374

struct its_vpe *vpe = NULL;

drivers/irqchip/irq-gic-v3-its.c

378

vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

3799

static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

3806

if (vpe->vpe_proxy_event == -1)

drivers/irqchip/irq-gic-v3-its.c

3809

its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);

drivers/irqchip/irq-gic-v3-its.c

3810

vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;

drivers/irqchip/irq-gic-v3-its.c

382

vpe = map->vpe;

drivers/irqchip/irq-gic-v3-its.c

3820

vpe_proxy.next_victim = vpe->vpe_proxy_event;

drivers/irqchip/irq-gic-v3-its.c

3822

vpe->vpe_proxy_event = -1;

drivers/irqchip/irq-gic-v3-its.c

3825

static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

3835

its_vpe_db_proxy_unmap_locked(vpe);

drivers/irqchip/irq-gic-v3-its.c

3840

static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

3847

if (vpe->vpe_proxy_event != -1)

drivers/irqchip/irq-gic-v3-its.c

385

if (vpe) {

drivers/irqchip/irq-gic-v3-its.c

3855

vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;

drivers/irqchip/irq-gic-v3-its.c

3856

vpe->vpe_proxy_event = vpe_proxy.next_victim;

drivers/irqchip/irq-gic-v3-its.c

3859

vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;

drivers/irqchip/irq-gic-v3-its.c

386

cpu = vpe_to_cpuid_lock(vpe, flags);

drivers/irqchip/irq-gic-v3-its.c

3860

its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);

drivers/irqchip/irq-gic-v3-its.c

3863

static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)

drivers/irqchip/irq-gic-v3-its.c

3876

gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);

drivers/irqchip/irq-gic-v3-its.c

3884

its_vpe_db_proxy_map_locked(vpe);

drivers/irqchip/irq-gic-v3-its.c

3887

its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);

drivers/irqchip/irq-gic-v3-its.c

3888

vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;

drivers/irqchip/irq-gic-v3-its.c

3893

static void its_vpe_4_1_invall_locked(int cpu, struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

3899

val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

3911

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

3921

if (!atomic_read(&vpe->vmapp_count)) {

drivers/irqchip/irq-gic-v3-its.c

3952

raw_spin_lock(&vpe->its_vm->vmapp_lock);

drivers/irqchip/irq-gic-v3-its.c

3954

from = vpe_to_cpuid_lock(vpe, &flags);

drivers/irqchip/irq-gic-v3-its.c

3974

vpe->col_idx = cpu;

drivers/irqchip/irq-gic-v3-its.c

3976

its_send_vmovp(vpe);

drivers/irqchip/irq-gic-v3-its.c

3980

its_vpe_4_1_invall_locked(cpu, vpe);

drivers/irqchip/irq-gic-v3-its.c

3982

its_vpe_db_proxy_move(vpe, from, cpu);

drivers/irqchip/irq-gic-v3-its.c

3986

vpe_to_cpuid_unlock(vpe, flags);

drivers/irqchip/irq-gic-v3-its.c

3989

raw_spin_unlock(&vpe->its_vm->vmapp_lock);

drivers/irqchip/irq-gic-v3-its.c

400

struct its_vpe *vpe = NULL;

drivers/irqchip/irq-gic-v3-its.c

4008

static void its_vpe_schedule(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4014

val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &

drivers/irqchip/irq-gic-v3-its.c

4023

val = virt_to_phys(page_address(vpe->vpt_page)) &

drivers/irqchip/irq-gic-v3-its.c

403

vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4039

val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;

drivers/irqchip/irq-gic-v3-its.c

4044

static void its_vpe_deschedule(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4051

vpe->idai = !!(val & GICR_VPENDBASER_IDAI);

drivers/irqchip/irq-gic-v3-its.c

4052

vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);

drivers/irqchip/irq-gic-v3-its.c

4055

static void its_vpe_invall(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4059

guard(raw_spinlock_irqsave)(&vpe->its_vm->vmapp_lock);

drivers/irqchip/irq-gic-v3-its.c

4065

if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])

drivers/irqchip/irq-gic-v3-its.c

407

vpe = map->vpe;

drivers/irqchip/irq-gic-v3-its.c

4072

its_send_vinvall(its, vpe);

drivers/irqchip/irq-gic-v3-its.c

4079

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4084

its_vpe_schedule(vpe);

drivers/irqchip/irq-gic-v3-its.c

4088

its_vpe_deschedule(vpe);

drivers/irqchip/irq-gic-v3-its.c

4096

its_vpe_invall(vpe);

drivers/irqchip/irq-gic-v3-its.c

410

if (vpe)

drivers/irqchip/irq-gic-v3-its.c

4104

static void its_vpe_send_cmd(struct its_vpe *vpe,

drivers/irqchip/irq-gic-v3-its.c

411

vpe_to_cpuid_unlock(vpe, flags);

drivers/irqchip/irq-gic-v3-its.c

4111

its_vpe_db_proxy_map_locked(vpe);

drivers/irqchip/irq-gic-v3-its.c

4112

cmd(vpe_proxy.dev, vpe->vpe_proxy_event);

drivers/irqchip/irq-gic-v3-its.c

4119

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4124

its_vpe_send_cmd(vpe, its_send_inv);

drivers/irqchip/irq-gic-v3-its.c

4150

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4158

rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;

drivers/irqchip/irq-gic-v3-its.c

4160

gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);

drivers/irqchip/irq-gic-v3-its.c

4162

gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);

drivers/irqchip/irq-gic-v3-its.c

4167

its_vpe_send_cmd(vpe, its_send_int);

drivers/irqchip/irq-gic-v3-its.c

4169

its_vpe_send_cmd(vpe, its_send_clear);

drivers/irqchip/irq-gic-v3-its.c

4210

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

422

static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4220

its_send_invdb(its, vpe);

drivers/irqchip/irq-gic-v3-its.c

4235

static void its_vpe_4_1_schedule(struct its_vpe *vpe,

drivers/irqchip/irq-gic-v3-its.c

424

if (valid_col(its->collections + vpe->col_idx))

drivers/irqchip/irq-gic-v3-its.c

4245

val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

425

return vpe;

drivers/irqchip/irq-gic-v3-its.c

4250

static void its_vpe_4_1_deschedule(struct its_vpe *vpe,

drivers/irqchip/irq-gic-v3-its.c

4269

raw_spin_lock_irqsave(&vpe->vpe_lock, flags);

drivers/irqchip/irq-gic-v3-its.c

4273

vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);

drivers/irqchip/irq-gic-v3-its.c

4274

raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);

drivers/irqchip/irq-gic-v3-its.c

4283

vpe->pending_last = true;

drivers/irqchip/irq-gic-v3-its.c

4287

static void its_vpe_4_1_invall(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4293

cpu = vpe_to_cpuid_lock(vpe, &flags);

drivers/irqchip/irq-gic-v3-its.c

4294

its_vpe_4_1_invall_locked(cpu, vpe);

drivers/irqchip/irq-gic-v3-its.c

4295

vpe_to_cpuid_unlock(vpe, flags);

drivers/irqchip/irq-gic-v3-its.c

4300

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4305

its_vpe_4_1_schedule(vpe, info);

drivers/irqchip/irq-gic-v3-its.c

4309

its_vpe_4_1_deschedule(vpe, info);

drivers/irqchip/irq-gic-v3-its.c

4317

its_vpe_4_1_invall(vpe);

drivers/irqchip/irq-gic-v3-its.c

4336

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4339

desc.its_vsgi_cmd.vpe = vpe;

drivers/irqchip/irq-gic-v3-its.c

4341

desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;

drivers/irqchip/irq-gic-v3-its.c

4342

desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;

drivers/irqchip/irq-gic-v3-its.c

4343

desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;

drivers/irqchip/irq-gic-v3-its.c

4356

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4358

vpe->sgi_config[d->hwirq].enabled = false;

drivers/irqchip/irq-gic-v3-its.c

4364

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4366

vpe->sgi_config[d->hwirq].enabled = true;

drivers/irqchip/irq-gic-v3-its.c

4391

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4395

val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

4408

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4428

cpu = vpe_to_cpuid_lock(vpe, &flags);

drivers/irqchip/irq-gic-v3-its.c

4431

writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);

drivers/irqchip/irq-gic-v3-its.c

4448

vpe_to_cpuid_unlock(vpe, flags);

drivers/irqchip/irq-gic-v3-its.c

4460

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4465

vpe->sgi_config[d->hwirq].priority = info->priority;

drivers/irqchip/irq-gic-v3-its.c

4466

vpe->sgi_config[d->hwirq].group = info->group;

drivers/irqchip/irq-gic-v3-its.c

4489

struct its_vpe *vpe = args;

drivers/irqchip/irq-gic-v3-its.c

4496

vpe->sgi_config[i].priority = 0;

drivers/irqchip/irq-gic-v3-its.c

4497

vpe->sgi_config[i].enabled = false;

drivers/irqchip/irq-gic-v3-its.c

4498

vpe->sgi_config[i].group = false;

drivers/irqchip/irq-gic-v3-its.c

4501

&its_sgi_irq_chip, vpe);

drivers/irqchip/irq-gic-v3-its.c

4526

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4538

vpe->sgi_config[d->hwirq].enabled = false;

drivers/irqchip/irq-gic-v3-its.c

4560

static int its_vpe_init(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4583

raw_spin_lock_init(&vpe->vpe_lock);

drivers/irqchip/irq-gic-v3-its.c

4584

vpe->vpe_id = vpe_id;

drivers/irqchip/irq-gic-v3-its.c

4585

vpe->vpt_page = vpt_page;

drivers/irqchip/irq-gic-v3-its.c

4586

atomic_set(&vpe->vmapp_count, 0);

drivers/irqchip/irq-gic-v3-its.c

4588

vpe->vpe_proxy_event = -1;

drivers/irqchip/irq-gic-v3-its.c

4593

static void its_vpe_teardown(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v3-its.c

4595

its_vpe_db_proxy_unmap(vpe);

drivers/irqchip/irq-gic-v3-its.c

4596

its_vpe_id_free(vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

4597

its_free_pending_table(vpe->vpt_page);

drivers/irqchip/irq-gic-v3-its.c

4612

struct its_vpe *vpe = irq_data_get_irq_chip_data(data);

drivers/irqchip/irq-gic-v3-its.c

4614

BUG_ON(vm != vpe->its_vm);

drivers/irqchip/irq-gic-v3-its.c

4617

its_vpe_teardown(vpe);

drivers/irqchip/irq-gic-v3-its.c

4684

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4688

vpe->col_idx = cpumask_first(cpu_online_mask);

drivers/irqchip/irq-gic-v3-its.c

4689

irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));

drivers/irqchip/irq-gic-v3-its.c

4703

its_send_vmapp(its, vpe, true);

drivers/irqchip/irq-gic-v3-its.c

4704

its_send_vinvall(its, vpe);

drivers/irqchip/irq-gic-v3-its.c

4713

struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-gic-v3-its.c

4727

its_send_vmapp(its, vpe, false);

drivers/irqchip/irq-gic-v3-its.c

4735

if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))

drivers/irqchip/irq-gic-v3-its.c

4736

gic_flush_dcache_to_poc(page_address(vpe->vpt_page),

drivers/irqchip/irq-gic-v3-its.c

483

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

487

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

493

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

501

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

508

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

515

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

519

struct its_vpe *vpe;

drivers/irqchip/irq-gic-v3-its.c

870

its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

874

return valid_vpe(its, desc->its_vinvall_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

881

struct its_vpe *vpe = valid_vpe(its, desc->its_vmapp_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

887

its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

891

alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);

drivers/irqchip/irq-gic-v3-its.c

898

vpe = NULL;

drivers/irqchip/irq-gic-v3-its.c

904

vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));

drivers/irqchip/irq-gic-v3-its.c

911

alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);

drivers/irqchip/irq-gic-v3-its.c

916

vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));

drivers/irqchip/irq-gic-v3-its.c

928

its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);

drivers/irqchip/irq-gic-v3-its.c

933

return vpe;

drivers/irqchip/irq-gic-v3-its.c

943

db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;

drivers/irqchip/irq-gic-v3-its.c

949

its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

956

return valid_vpe(its, desc->its_vmapti_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

966

db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;

drivers/irqchip/irq-gic-v3-its.c

972

its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

979

return valid_vpe(its, desc->its_vmovi_cmd.vpe);

drivers/irqchip/irq-gic-v3-its.c

992

its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);

drivers/irqchip/irq-gic-v3-its.c

997

its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);

drivers/irqchip/irq-gic-v4.c

119

static int its_alloc_vcpu_sgis(struct its_vpe *vpe, int idx)

drivers/irqchip/irq-gic-v4.c

131

vpe->fwnode = irq_domain_alloc_named_id_fwnode(name, idx);

drivers/irqchip/irq-gic-v4.c

132

if (!vpe->fwnode)

drivers/irqchip/irq-gic-v4.c

138

vpe->sgi_domain = irq_domain_create_linear(vpe->fwnode, 16,

drivers/irqchip/irq-gic-v4.c

139

sgi_domain_ops, vpe);

drivers/irqchip/irq-gic-v4.c

140

if (!vpe->sgi_domain)

drivers/irqchip/irq-gic-v4.c

143

sgi_base = irq_domain_alloc_irqs(vpe->sgi_domain, 16, NUMA_NO_NODE, vpe);

drivers/irqchip/irq-gic-v4.c

150

if (vpe->sgi_domain)

drivers/irqchip/irq-gic-v4.c

151

irq_domain_remove(vpe->sgi_domain);

drivers/irqchip/irq-gic-v4.c

152

if (vpe->fwnode)

drivers/irqchip/irq-gic-v4.c

153

irq_domain_free_fwnode(vpe->fwnode);

drivers/irqchip/irq-gic-v4.c

229

static int its_send_vpe_cmd(struct its_vpe *vpe, struct its_cmd_info *info)

drivers/irqchip/irq-gic-v4.c

231

return irq_set_vcpu_affinity(vpe->irq, info);

drivers/irqchip/irq-gic-v4.c

234

int its_make_vpe_non_resident(struct its_vpe *vpe, bool db)

drivers/irqchip/irq-gic-v4.c

236

struct irq_desc *desc = irq_to_desc(vpe->irq);

drivers/irqchip/irq-gic-v4.c

249

enable_irq(vpe->irq);

drivers/irqchip/irq-gic-v4.c

252

ret = its_send_vpe_cmd(vpe, &info);

drivers/irqchip/irq-gic-v4.c

254

vpe->resident = false;

drivers/irqchip/irq-gic-v4.c

256

vpe->ready = false;

drivers/irqchip/irq-gic-v4.c

261

int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en)

drivers/irqchip/irq-gic-v4.c

274

disable_irq_nosync(vpe->irq);

drivers/irqchip/irq-gic-v4.c

277

ret = its_send_vpe_cmd(vpe, &info);

drivers/irqchip/irq-gic-v4.c

279

vpe->resident = true;

drivers/irqchip/irq-gic-v4.c

284

int its_commit_vpe(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v4.c

293

ret = its_send_vpe_cmd(vpe, &info);

drivers/irqchip/irq-gic-v4.c

295

vpe->ready = true;

drivers/irqchip/irq-gic-v4.c

301

int its_invall_vpe(struct its_vpe *vpe)

drivers/irqchip/irq-gic-v4.c

307

return its_send_vpe_cmd(vpe, &info);

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

1634

struct virtchnl_pf_event *vpe)

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

1637

return vpe->event_data.link_event_adv.link_status;

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

1639

return vpe->event_data.link_event.link_status;

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

1651

struct virtchnl_pf_event *vpe)

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

1655

vpe->event_data.link_event_adv.link_speed;

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

1657

adapter->link_speed = vpe->event_data.link_event.link_speed;

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

2299

struct virtchnl_pf_event *vpe =

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

2301

bool link_up = iavf_get_vpe_link_status(adapter, vpe);

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

2303

switch (vpe->event) {

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

2305

iavf_set_adapter_link_speed_from_vpe(adapter, vpe);

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

2350

vpe->event);

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

85

struct virtchnl_pf_event *vpe =

drivers/net/ethernet/intel/iavf/iavf_virtchnl.c

88

if (vpe->event != VIRTCHNL_EVENT_RESET_IMPENDING)

include/linux/irqchip/arm-gic-v4.h

106

struct its_vpe *vpe;

include/linux/irqchip/arm-gic-v4.h

143

int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en);

include/linux/irqchip/arm-gic-v4.h

144

int its_make_vpe_non_resident(struct its_vpe *vpe, bool db);

include/linux/irqchip/arm-gic-v4.h

145

int its_commit_vpe(struct its_vpe *vpe);

include/linux/irqchip/arm-gic-v4.h

146

int its_invall_vpe(struct its_vpe *vpe);