drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

136

dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

138

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

200

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

201

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

202

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

203

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

204

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

214

dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

216

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

347

return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

661

WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

677

WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

722

rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

724

rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

741

wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

743

wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

776

WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

778

WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

895

context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

900

WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

100

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

110

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

112

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_CHECKSUM));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

117

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE1_CHECKSUM));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

123

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS2));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

129

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS6));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

145

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

147

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

152

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

154

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

162

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

167

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

169

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

175

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

192

rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

196

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

199

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

200

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

201

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

202

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

205

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

207

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

212

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

213

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

218

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

219

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

220

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

222

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

224

doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

226

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

228

doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

230

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

236

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

238

ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

240

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

257

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

261

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

283

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

287

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

69

ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

71

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

73

reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2));

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

75

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2), reg_data);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

82

f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

94

f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

109

vpe_colla_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

112

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL), vpe_colla_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

114

vpe_colla_cfg = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

119

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG), vpe_colla_cfg);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

136

ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

138

ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

143

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1), ret);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

145

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

161

f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

186

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

188

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

196

WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

218

rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

222

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

225

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

226

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

227

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

228

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

231

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

233

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

238

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

239

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

244

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

245

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

246

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

248

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

250

doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

252

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

254

doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

256

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

262

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

264

ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

266

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

284

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

286

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

291

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1), queue_reset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

295

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

318

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

320

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

326

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1), vpe_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

328

WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

79

f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

82

WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl);