arch/x86/events/core.c

1269

hwc->config_base = x86_pmu_config_addr(hwc->idx);

arch/x86/events/core.c

1600

rdmsrq(x86_pmu_config_addr(idx), pmc_ctrl);

arch/x86/events/core.c

230

if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))

arch/x86/events/core.c

239

release_evntsel_nmi(x86_pmu_config_addr(i));

arch/x86/events/core.c

257

release_evntsel_nmi(x86_pmu_config_addr(i));

arch/x86/events/core.c

281

reg = x86_pmu_config_addr(i);

arch/x86/events/core.c

716

rdmsrq(x86_pmu_config_addr(idx), val);

arch/x86/events/core.c

720

wrmsrq(x86_pmu_config_addr(idx), val);

arch/x86/events/core.c

722

wrmsrq(x86_pmu_config_addr(idx + 1), 0);

arch/x86/events/intel/core.c

3434

wrmsrq_safe(x86_pmu_config_addr(idx), 0ull);

arch/x86/events/intel/core.c

5084

arr[idx].msr = x86_pmu_config_addr(idx);

arch/x86/events/intel/p4.c

1400

reg = x86_pmu_config_addr(i);

arch/x86/events/perf_event.h

1281

wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);

arch/x86/events/perf_event.h

1302

wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0);