arch/x86/kvm/vmx/pmu_intel.c

672

vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

673

vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

675

vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

678

vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

679

vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/vmx.c

4182

vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4199

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4200

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4201

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4202

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4204

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4205

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4237

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i,

arch/x86/kvm/vmx/vmx.c

4239

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4243

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i,

arch/x86/kvm/vmx/vmx.c

4245

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i,

arch/x86/kvm/vmx/vmx.c

4250

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR0 + i,

arch/x86/kvm/vmx/vmx.c

4253

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR0 + i,

arch/x86/kvm/vmx/vmx.c

4257

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_STATUS,

arch/x86/kvm/vmx/vmx.c

4259

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,

arch/x86/kvm/vmx/vmx.c

4261

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,

arch/x86/kvm/vmx/vmx.c

4299

vmx_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4303

vmx_set_intercept_for_msr(vcpu, MSR_IA32_XFD_ERR, MSR_TYPE_R,

arch/x86/kvm/vmx/vmx.c

4307

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W,

arch/x86/kvm/vmx/vmx.c

4311

vmx_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,

arch/x86/kvm/vmx/vmx.c

4317

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4318

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4319

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4320

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4327

vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4328

vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.h

381

void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set);

arch/x86/kvm/vmx/vmx.h

386

vmx_set_intercept_for_msr(vcpu, msr, type, false);

arch/x86/kvm/vmx/vmx.h

392

vmx_set_intercept_for_msr(vcpu, msr, type, true);