wrmsrq_on_cpu
int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
ret = wrmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS,
EXPORT_SYMBOL(wrmsrq_on_cpu);
int ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
wrmsrq_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
ret = wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_CLASS_CONFIG, state ? 1 : 0);
return wrmsrq_on_cpu(cpu, MSR_AMD_WORKLOAD_HRST, 0x1);
wrmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT,
ret = wrmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, cap);