wrmsrl
wrmsrl(hwc->event_base, 0);
wrmsrl(msr_b + msr_offset, mask);
wrmsrl(msr_c + msr_offset, reload);
wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full);
wrmsrl(MSR_AMD_WORKLOAD_HRST, 0x1);
wrmsrl(gp_counter_msr(i), pmc->counter);
wrmsrl(gp_eventsel_msr(i), pmc->eventsel_hw);
wrmsrl(fixed_counter_msr(i), pmc->counter);
wrmsrl(MSR_IA32_XSS, kvm_host.xss);
wrmsrl(MSR_KERNEL_GS_BASE, vt->msr_host_kernel_gs_base);
wrmsrl(reg_table[i].msr_addr, *reg64);
wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_val);