wrl
wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
wrl(ep, REG_MIIDATA, data);
wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
wrl(ep, REG_TXDENQ, 1);
wrl(ep, REG_INTEN, REG_INTEN_TX);
wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
wrl(ep, REG_RXDQBADD, addr);
wrl(ep, REG_RXDCURADD, addr);
wrl(ep, REG_RXSTSQBADD, addr);
wrl(ep, REG_RXSTSQCURADD, addr);
wrl(ep, REG_TXDQBADD, addr);
wrl(ep, REG_TXDQCURADD, addr);
wrl(ep, REG_TXSTSQBADD, addr);
wrl(ep, REG_TXSTSQCURADD, addr);
wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
wrl(ep, REG_GIINTMSK, 0);
wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
wrl(ep, REG_AFP, 0);
wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
wrl(ep, REG_GIINTMSK, 0);
wrl(mp, off, v);
wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
wrl(mp, PHY_ADDR, data);
wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
wrl(pep, INT_MASK, 0);
wrl(pep, INT_CAUSE, 0);
wrl(pep, INT_W_CLEAR, 0);
wrl(pep, INT_MASK, ALL_INTS);
wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
wrl(pep, HTPR, pep->htpr_dma);
wrl(pep, PORT_CONFIG, val);
wrl(pep, MAC_ADDR_HIGH, mac_h);
wrl(pep, MAC_ADDR_LOW, mac_l);
wrl(pep, ETH_C_TX_DESC_1,
wrl(pep, ETH_C_RX_DESC_0,
wrl(pep, ETH_F_RX_DESC_0,
wrl(pep, INT_CAUSE, 0);
wrl(pep, INT_MASK, ALL_INTS);
wrl(pep, PORT_CONFIG, val);
wrl(pep, SDMA_CMD, val);
wrl(pep, INT_MASK, 0);
wrl(pep, INT_CAUSE, 0);
wrl(pep, PORT_CONFIG, val);
wrl(pep, INT_CAUSE, ~icr);
wrl(pep, INT_MASK, 0);
wrl(pep, PORT_CONFIG_EXT,
wrl(pep, PORT_CONFIG, cfg);
wrl(pep, PORT_CONFIG_EXT, cfgext);
wrl(pep, INT_MASK, 0);
wrl(pep, INT_CAUSE, 0);
wrl(pep, INT_W_CLEAR, 0);
wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40);
wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040);
wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010);
wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32);
wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
wrl(USB_CMD, rdl(USB_CMD) & ~USB_CMD_RUN);
wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
wrl(USB_MODE, USB_MODE_SDIS | USB_MODE_HOST);
wrl(USB_WINDOW_CTRL(i), 0);
wrl(USB_WINDOW_BASE(i), 0);
wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
wrl(USB_WINDOW_BASE(i), cs->base);
wrl(USB_SBUSCFG, USB_SBUSCFG_DEF_VAL);
wrl(USB_CAUSE, 0);
wrl(USB_MASK, 0);
wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00);