writel_bits_relaxed
writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |
writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR,
writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR,
writel_bits_relaxed(OSD_MALI_SRC_EN, OSD_MALI_SRC_EN,
writel_bits_relaxed(3 << 8, 3 << 8,
writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1,
writel_bits_relaxed(0x3, 0,
writel_bits_relaxed(0xf << 8, 0,
writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
writel_bits_relaxed(BIT(15), BIT(15),
writel_bits_relaxed(BIT(15), BIT(15),
writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
writel_bits_relaxed(MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN,
writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFIFO_EN,
writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
writel_bits_relaxed(0x3, 0,
writel_bits_relaxed(OSD1_AFBCD_DEC_ENABLE, 0,
writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET,
writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, 0,
writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0,
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1,
writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 |
writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1,
writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1,
writel_bits_relaxed(0xff, 0xff,
writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH,
writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0,
writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, L_GAMMA_CNTL_PORT_EN,
writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0,
writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI |
writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
writel_bits_relaxed(3 << 30, m[21] << 30,
writel_bits_relaxed(7 << 16, m[22] << 16,
writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
writel_bits_relaxed(BIT(1), 0,
writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0,
writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0,
writel_bits_relaxed(0x7 << 29, 7 << 29,
writel_bits_relaxed(0x7 << 29, 0,
writel_bits_relaxed(7 << 27, 7 << 27,
writel_bits_relaxed(7 << 27, 0,
writel_bits_relaxed(BIT(31), BIT(31),
writel_bits_relaxed(VIU_SW_RESET_OSD1, VIU_SW_RESET_OSD1,
writel_bits_relaxed(VIU_SW_RESET_OSD1, 0,
writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN,
writel_bits_relaxed(VIU_OSD1_MALI_AFBCD_A_REORDER |
writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD,
writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, 0,
writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN, 0,
writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x90),
writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x00),
writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0,
writel_bits_relaxed(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc),
writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f,
writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
writel_bits_relaxed(0xff << 16, 0xff << 16,
writel_bits_relaxed(cfg, enable ? cfg : 0,
writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET,
writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK,
writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0,
writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, SPICC_BURSTLENGTH_MASK,
writel_bits_relaxed(SPICC_SMC, 0, spicc->base + SPICC_CONREG);
writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
writel_bits_relaxed(SPICC_SMC, SPICC_SMC, spicc->base + SPICC_CONREG);
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
writel_bits_relaxed(SPICC_LBC_W1,