arch/arc/include/asm/io.h

203

#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })

arch/arm/include/asm/io.h

288

#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })

arch/arm/kernel/smp_scu.c

86

writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);

arch/arm/mach-sa1100/neponset.c

321

writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);

arch/csky/include/asm/io.h

25

#define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); })

arch/csky/include/asm/io.h

29

#define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); mb(); })

arch/sh/include/asm/io.h

53

#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })

drivers/acpi/cppc_acpi.c

1152

writeb_relaxed(val, vaddr);

drivers/base/regmap/regmap-mmio.c

76

writeb_relaxed(val, ctx->regs + reg);

drivers/clocksource/timer-gxp.c

51

writeb_relaxed(MASK_TCS_TC, timer->control);

drivers/clocksource/timer-gxp.c

53

writeb_relaxed(MASK_TCS_TC | MASK_TCS_ENABLE, timer->control);

drivers/clocksource/timer-gxp.c

65

writeb_relaxed(MASK_TCS_TC, timer->control);

drivers/dma/ti/dma-crossbar.c

60

writeb_relaxed(val, iomem + (63 - event % 4));

drivers/dma/ti/dma-crossbar.c

62

writeb_relaxed(val, iomem + event);

drivers/gpio/gpio-ep93xx.c

64

writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);

drivers/gpio/gpio-ep93xx.c

66

writeb_relaxed(eic->int_type2,

drivers/gpio/gpio-ep93xx.c

69

writeb_relaxed(eic->int_type1,

drivers/gpio/gpio-ep93xx.c

72

writeb_relaxed(eic->int_unmasked & eic->int_enabled,

drivers/gpio/gpio-msc313.c

499

writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);

drivers/gpio/gpio-msc313.c

517

writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);

drivers/gpio/gpio-msc313.c

532

writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);

drivers/gpio/gpio-msc313.c

714

writeb_relaxed(gpio->saved[i], gpio->base + gpio->gpio_data->offsets[i]);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

138

writeb_relaxed(val, ptr);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

139

writeb_relaxed(val >> 8, ptr + 1);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

140

writeb_relaxed(val >> 16, ptr + 2);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

141

writeb_relaxed(val >> 24, ptr + 3);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

244

writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL,

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

254

writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

266

writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

267

writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

280

writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

353

writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

357

writeb_relaxed(~0, base + HDMI_AHB_DMA_POL);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

358

writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

361

writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

362

writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

370

writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

382

writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

459

writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

460

writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

461

writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

553

writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,

drivers/hwtracing/coresight/coresight-stm.c

333

writeb_relaxed(*(u8 *)data, addr);

drivers/hwtracing/intel_th/sth.c

113

writeb_relaxed(0, outp);

drivers/hwtracing/intel_th/sth.c

55

writeb_relaxed(*(u8 *)payload, dest);

drivers/hwtracing/intel_th/sth.c

96

writeb_relaxed(*payload, sth->base + reg);

drivers/i2c/busses/i2c-at91-master.c

161

writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);

drivers/i2c/busses/i2c-at91-slave.c

30

writeb_relaxed(value, dev->base + AT91_TWI_THR);

drivers/i2c/busses/i2c-at91-slave.c

45

writeb_relaxed(value, dev->base + AT91_TWI_THR);

drivers/i2c/busses/i2c-digicolor.c

132

writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);

drivers/i2c/busses/i2c-digicolor.c

133

writeb_relaxed(!!enable, i2c->regs + II_INTENABLE);

drivers/i2c/busses/i2c-digicolor.c

165

writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR);

drivers/i2c/busses/i2c-digicolor.c

262

writeb_relaxed(II_CONTROL_LOCAL_RESET, i2c->regs + II_CONTROL);

drivers/i2c/busses/i2c-digicolor.c

264

writeb_relaxed(0, i2c->regs + II_CONTROL);

drivers/i2c/busses/i2c-digicolor.c

273

writeb_relaxed(clocktime - 1, i2c->regs + II_CLOCKTIME);

drivers/i2c/busses/i2c-digicolor.c

73

writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND);

drivers/i2c/busses/i2c-digicolor.c

88

writeb_relaxed(data, i2c->regs + II_DATA);

drivers/i2c/busses/i2c-stm32f7.c

793

writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);

drivers/irqchip/irq-gic-v3.c

594

writeb_relaxed(prio, base + offset + index);

drivers/irqchip/irq-gic.c

814

writeb_relaxed(gic_cpu_map[cpu], reg);

drivers/mfd/omap-usb-tll.c

125

writeb_relaxed(val, base + reg);

drivers/mmc/host/sdhci-msm.c

2269

writeb_relaxed(val, host->ioaddr + reg);

drivers/mmc/host/sdhci-sprd.c

172

writeb_relaxed(val, host->ioaddr + reg);

drivers/mmc/host/sdhci-sprd.c

392

writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);

drivers/mmc/host/sdhci-sprd.c

397

writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);

drivers/mtd/nand/raw/fsmc_nand.c

575

writeb_relaxed(buf[i], host->data_va);

drivers/mtd/nand/raw/fsmc_nand.c

653

writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);

drivers/mtd/nand/raw/fsmc_nand.c

658

writeb_relaxed(instr->ctx.addr.addrs[i],

drivers/mtd/nand/raw/stm32_fmc2_nand.c

1255

writeb_relaxed(*(u8 *)buf, io_addr_w);

drivers/mtd/nand/raw/stm32_fmc2_nand.c

1283

writeb_relaxed(*(u8 *)buf, io_addr_w);

drivers/mtd/nand/raw/stm32_fmc2_nand.c

1337

writeb_relaxed(instr->ctx.cmd.opcode,

drivers/mtd/nand/raw/stm32_fmc2_nand.c

1343

writeb_relaxed(instr->ctx.addr.addrs[i],

drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c

173

writeb_relaxed(1, &zone_data->trigger.vf_pf_channel.addr_valid);

drivers/pci/controller/pcie-altera.c

173

writeb_relaxed(value, pcie->cra_base + reg);

drivers/pci/controller/pcie-altera.c

517

writeb_relaxed(value, addr);

drivers/pci/controller/pcie-rzg3s-host.c

1052

writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);

drivers/pci/controller/pcie-rzg3s-host.c

1053

writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);

drivers/pci/controller/pcie-rzg3s-host.c

1054

writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);

drivers/phy/st/phy-miphy28lp.c

1001

writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);

drivers/phy/st/phy-miphy28lp.c

1002

writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);

drivers/phy/st/phy-miphy28lp.c

1003

writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);

drivers/phy/st/phy-miphy28lp.c

1004

writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);

drivers/phy/st/phy-miphy28lp.c

1005

writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);

drivers/phy/st/phy-miphy28lp.c

1006

writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);

drivers/phy/st/phy-miphy28lp.c

1007

writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);

drivers/phy/st/phy-miphy28lp.c

1008

writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);

drivers/phy/st/phy-miphy28lp.c

366

writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

369

writeb_relaxed(val, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

371

writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

376

writeb_relaxed(val, base + MIPHY_CONTROL);

drivers/phy/st/phy-miphy28lp.c

379

writeb_relaxed(val, base + MIPHY_CONTROL);

drivers/phy/st/phy-miphy28lp.c

390

writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);

drivers/phy/st/phy-miphy28lp.c

391

writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);

drivers/phy/st/phy-miphy28lp.c

394

writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);

drivers/phy/st/phy-miphy28lp.c

395

writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);

drivers/phy/st/phy-miphy28lp.c

396

writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);

drivers/phy/st/phy-miphy28lp.c

397

writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);

drivers/phy/st/phy-miphy28lp.c

398

writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);

drivers/phy/st/phy-miphy28lp.c

400

writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);

drivers/phy/st/phy-miphy28lp.c

403

writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);

drivers/phy/st/phy-miphy28lp.c

410

writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);

drivers/phy/st/phy-miphy28lp.c

413

writeb_relaxed(0x00, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

414

writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);

drivers/phy/st/phy-miphy28lp.c

415

writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);

drivers/phy/st/phy-miphy28lp.c

416

writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);

drivers/phy/st/phy-miphy28lp.c

417

writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);

drivers/phy/st/phy-miphy28lp.c

420

writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);

drivers/phy/st/phy-miphy28lp.c

434

writeb_relaxed(gen->bank, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

435

writeb_relaxed(gen->speed, base + MIPHY_SPEED);

drivers/phy/st/phy-miphy28lp.c

436

writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);

drivers/phy/st/phy-miphy28lp.c

437

writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);

drivers/phy/st/phy-miphy28lp.c

440

writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);

drivers/phy/st/phy-miphy28lp.c

441

writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);

drivers/phy/st/phy-miphy28lp.c

444

writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);

drivers/phy/st/phy-miphy28lp.c

445

writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);

drivers/phy/st/phy-miphy28lp.c

446

writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);

drivers/phy/st/phy-miphy28lp.c

447

writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);

drivers/phy/st/phy-miphy28lp.c

448

writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);

drivers/phy/st/phy-miphy28lp.c

461

writeb_relaxed(gen->bank, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

462

writeb_relaxed(gen->speed, base + MIPHY_SPEED);

drivers/phy/st/phy-miphy28lp.c

463

writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);

drivers/phy/st/phy-miphy28lp.c

464

writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);

drivers/phy/st/phy-miphy28lp.c

467

writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);

drivers/phy/st/phy-miphy28lp.c

468

writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);

drivers/phy/st/phy-miphy28lp.c

469

writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);

drivers/phy/st/phy-miphy28lp.c

471

writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);

drivers/phy/st/phy-miphy28lp.c

474

writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);

drivers/phy/st/phy-miphy28lp.c

475

writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);

drivers/phy/st/phy-miphy28lp.c

476

writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);

drivers/phy/st/phy-miphy28lp.c

477

writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);

drivers/phy/st/phy-miphy28lp.c

498

writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

500

writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);

drivers/phy/st/phy-miphy28lp.c

501

writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);

drivers/phy/st/phy-miphy28lp.c

502

writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);

drivers/phy/st/phy-miphy28lp.c

505

writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

507

writeb_relaxed(0x00, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

508

writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);

drivers/phy/st/phy-miphy28lp.c

509

writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

512

writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);

drivers/phy/st/phy-miphy28lp.c

526

writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

527

writeb_relaxed(0x00, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

528

writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

531

writeb_relaxed(val, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

533

writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);

drivers/phy/st/phy-miphy28lp.c

534

writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);

drivers/phy/st/phy-miphy28lp.c

535

writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);

drivers/phy/st/phy-miphy28lp.c

536

writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

537

writeb_relaxed(0x00, base + MIPHY_RESET);

drivers/phy/st/phy-miphy28lp.c

538

writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);

drivers/phy/st/phy-miphy28lp.c

539

writeb_relaxed(0x00, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

540

writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);

drivers/phy/st/phy-miphy28lp.c

541

writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);

drivers/phy/st/phy-miphy28lp.c

542

writeb_relaxed(0x00, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

543

writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

544

writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);

drivers/phy/st/phy-miphy28lp.c

545

writeb_relaxed(0x00, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

560

writeb_relaxed(val, base + MIPHY_BOUNDARY_2);

drivers/phy/st/phy-miphy28lp.c

564

writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);

drivers/phy/st/phy-miphy28lp.c

567

writeb_relaxed(val, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

571

writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);

drivers/phy/st/phy-miphy28lp.c

572

writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);

drivers/phy/st/phy-miphy28lp.c

573

writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);

drivers/phy/st/phy-miphy28lp.c

576

writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

579

writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

582

writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

598

writeb_relaxed(val, base + MIPHY_BOUNDARY_2);

drivers/phy/st/phy-miphy28lp.c

602

writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);

drivers/phy/st/phy-miphy28lp.c

605

writeb_relaxed(val, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

608

writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);

drivers/phy/st/phy-miphy28lp.c

609

writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);

drivers/phy/st/phy-miphy28lp.c

612

writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);

drivers/phy/st/phy-miphy28lp.c

613

writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);

drivers/phy/st/phy-miphy28lp.c

616

writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

619

writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

622

writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

629

writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);

drivers/phy/st/phy-miphy28lp.c

649

writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);

drivers/phy/st/phy-miphy28lp.c

652

writeb_relaxed(0x00, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

664

writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);

drivers/phy/st/phy-miphy28lp.c

692

writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);

drivers/phy/st/phy-miphy28lp.c

695

writeb_relaxed(0x00, base + MIPHY_CONF_RESET);

drivers/phy/st/phy-miphy28lp.c

725

writeb_relaxed(0x00, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

728

writeb_relaxed(val, base + MIPHY_SPEED);

drivers/phy/st/phy-miphy28lp.c

731

writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);

drivers/phy/st/phy-miphy28lp.c

732

writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);

drivers/phy/st/phy-miphy28lp.c

733

writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);

drivers/phy/st/phy-miphy28lp.c

737

writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);

drivers/phy/st/phy-miphy28lp.c

738

writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);

drivers/phy/st/phy-miphy28lp.c

739

writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);

drivers/phy/st/phy-miphy28lp.c

742

writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);

drivers/phy/st/phy-miphy28lp.c

743

writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);

drivers/phy/st/phy-miphy28lp.c

744

writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);

drivers/phy/st/phy-miphy28lp.c

747

writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);

drivers/phy/st/phy-miphy28lp.c

752

writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);

drivers/phy/st/phy-miphy28lp.c

755

writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);

drivers/phy/st/phy-miphy28lp.c

756

writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);

drivers/phy/st/phy-miphy28lp.c

759

writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);

drivers/phy/st/phy-miphy28lp.c

762

writeb_relaxed(0x00, base + MIPHY_CONF);

drivers/phy/st/phy-miphy28lp.c

765

writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);

drivers/phy/st/phy-miphy28lp.c

766

writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);

drivers/phy/st/phy-miphy28lp.c

769

writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);

drivers/phy/st/phy-miphy28lp.c

770

writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);

drivers/phy/st/phy-miphy28lp.c

773

writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

776

writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

779

writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);

drivers/phy/st/phy-miphy28lp.c

782

writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);

drivers/phy/st/phy-miphy28lp.c

786

writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);

drivers/phy/st/phy-miphy28lp.c

787

writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);

drivers/phy/st/phy-miphy28lp.c

788

writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);

drivers/phy/st/phy-miphy28lp.c

961

writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */

drivers/phy/st/phy-miphy28lp.c

962

writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */

drivers/phy/st/phy-miphy28lp.c

963

writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */

drivers/phy/st/phy-miphy28lp.c

964

writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */

drivers/phy/st/phy-miphy28lp.c

965

writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */

drivers/phy/st/phy-miphy28lp.c

966

writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */

drivers/phy/st/phy-miphy28lp.c

993

writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);

drivers/phy/st/phy-miphy28lp.c

994

writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);

drivers/phy/st/phy-miphy28lp.c

995

writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);

drivers/phy/st/phy-miphy28lp.c

996

writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);

drivers/phy/st/phy-miphy28lp.c

997

writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);

drivers/phy/st/phy-miphy28lp.c

998

writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);

drivers/pinctrl/pinctrl-digicolor.c

138

writeb_relaxed(reg, pmap->regs + reg_off);

drivers/pinctrl/pinctrl-digicolor.c

179

writeb_relaxed(drive, pmap->regs + reg_off);

drivers/pinctrl/pinctrl-digicolor.c

201

writeb_relaxed(drive, pmap->regs + reg_off);

drivers/pinctrl/pinctrl-digicolor.c

233

writeb_relaxed(output, pmap->regs + reg_off);

drivers/rtc/rtc-digicolor.c

144

writeb_relaxed(!!alarm->enabled, rtc->regs + DC_RTC_INTENABLE);

drivers/rtc/rtc-digicolor.c

153

writeb_relaxed(!!enabled, rtc->regs + DC_RTC_INTENABLE);

drivers/rtc/rtc-digicolor.c

170

writeb_relaxed(1, rtc->regs + DC_RTC_INTFLAG_CLEAR);

drivers/rtc/rtc-digicolor.c

47

writeb_relaxed((cmds[i] & DC_RTC_CMD_MASK) | DC_RTC_GO_BUSY,

drivers/spi/spi-at91-usart.c

76

writeb_relaxed((value), (port)->regs + US_##reg)

drivers/spi/spi-axiado.c

55

writeb_relaxed(val, xspi->regs + offset);

drivers/spi/spi-sprd.c

335

writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);

drivers/spi/spi-stm32-ospi.c

166

writeb_relaxed(*((u8 *)val), addr);

drivers/spi/spi-stm32-qspi.c

169

writeb_relaxed(*((u8 *)val), addr);

drivers/spi/spi-stm32.c

474

writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);

drivers/spi/spi-stm32.c

632

writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR);

drivers/spi/spi-stm32.c

661

writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR);

drivers/spi/spi-stm32.c

696

writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);

drivers/tty/serial/digicolor-usart.c

100

writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);

drivers/tty/serial/digicolor-usart.c

108

writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);

drivers/tty/serial/digicolor-usart.c

116

writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);

drivers/tty/serial/digicolor-usart.c

127

writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET);

drivers/tty/serial/digicolor-usart.c

192

writeb_relaxed(port->x_char, port->membase + UA_EMI_REC);

drivers/tty/serial/digicolor-usart.c

222

writeb_relaxed(UA_INT_RX | UA_INT_TX,

drivers/tty/serial/digicolor-usart.c

258

writeb_relaxed(UA_ENABLE_ENABLE, port->membase + UA_ENABLE);

drivers/tty/serial/digicolor-usart.c

259

writeb_relaxed(UA_CONTROL_SOFT_RESET, port->membase + UA_CONTROL);

drivers/tty/serial/digicolor-usart.c

260

writeb_relaxed(0, port->membase + UA_CONTROL);

drivers/tty/serial/digicolor-usart.c

262

writeb_relaxed(UA_CONFIG_FIFO_RX_FIFO_MODE

drivers/tty/serial/digicolor-usart.c

265

writeb_relaxed(UA_STATUS_FIFO_RX_INT_ALMOST,

drivers/tty/serial/digicolor-usart.c

267

writeb_relaxed(UA_CONTROL_RX_ENABLE | UA_CONTROL_TX_ENABLE,

drivers/tty/serial/digicolor-usart.c

269

writeb_relaxed(UA_INT_TX | UA_INT_RX,

drivers/tty/serial/digicolor-usart.c

282

writeb_relaxed(0, port->membase + UA_ENABLE);

drivers/tty/serial/digicolor-usart.c

340

writeb_relaxed(config, port->membase + UA_CONFIG);

drivers/tty/serial/digicolor-usart.c

341

writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO);

drivers/tty/serial/digicolor-usart.c

342

writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI);

drivers/tty/serial/digicolor-usart.c

389

writeb_relaxed(ch, port->membase + UA_EMI_REC);

drivers/tty/serial/samsung_tty.c

188

writeb_relaxed(val, portaddr(port, reg));

include/asm-generic/io.h

381

#ifndef writeb_relaxed

include/asm-generic/io.h

382

#define writeb_relaxed writeb_relaxed

rust/helpers/io.c

90

writeb_relaxed(value, addr);

tools/include/asm-generic/io.h

314

#ifndef writeb_relaxed

tools/include/asm-generic/io.h

315

#define writeb_relaxed writeb_relaxed