writereg
void (*writereg)(struct videocodec *codec, __u16 reg, __u32 value);
m->writereg = zr36060_write;
m->writereg = zr36050_write;
m->writereg = zr36016_write;
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
if ((ptr->codec->master_data->writereg) && (ptr->codec->master_data->readreg)) {
ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F);
if (ptr->codec->master_data->writereg) {
ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F);
ptr->codec->master_data->writereg(ptr->codec, ZR016_IDATA, value & 0x0FF);
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
if (ptr->codec->master_data->writereg)
ptr->codec->master_data->writereg(ptr->codec, reg, value);
writereg(&ll->rap, LE_CSR1);
writereg(&ll->rdp, (leptr & 0xFFFF));
writereg(&ll->rap, LE_CSR2);
writereg(&ll->rdp, leptr >> 16);
writereg(&ll->rap, LE_CSR3);
writereg(&ll->rdp, lp->busmaster_regval);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_INIT);
writereg(&ll->rdp, LE_C0_IDON);
writereg(&ll->rdp, LE_C0_STRT);
writereg(&ll->rdp, LE_C0_INEA);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_STOP);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_STOP);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT));
writereg(&ll->rdp, LE_C0_BABL | LE_C0_ERR | LE_C0_MISS |
writereg(&ll->rdp, LE_C0_STOP);
writereg(&ll->rdp, LE_C0_INEA);
writereg(&ll->rdp, LE_C0_INEA);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_STOP);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_STOP);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_STOP);
writereg(&ll->rdp, LE_C0_INEA | LE_C0_TDMD);
writereg(&ll->rap, LE_CSR0);
writereg(&ll->rdp, LE_C0_STOP);
writereg(dev, PP_LineCTL, lp->linectl | AUTO_AUI_10BASET);
writereg(dev, PP_LineCTL,
writereg(dev, PP_RxCTL, DEF_RX_ACCEPT);
writereg(dev, PP_RxCFG, lp->curr_rx_cfg);
writereg(dev, PP_TxCFG, (TX_LOST_CRS_ENBL |
writereg(dev, PP_BufCFG, (READY_FOR_TX_ENBL |
writereg(dev, PP_BusCTL, (ENABLE_IRQ
writereg(dev, PP_RxCFG, 0);
writereg(dev, PP_TxCFG, 0);
writereg(dev, PP_BufCFG, 0);
writereg(dev, PP_BusCTL, 0);
writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode);
writereg(dev, PP_RxCFG, cfg);
writereg(dev, PP_IA + i * 2,
writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD);
writereg(dev, PP_CS8900_ISAINT, i);
writereg(dev, PP_CS8920_ISAINT, irq);
writereg(dev, PP_CS8900_ISADMA, dma - 5);
writereg(dev, PP_CS8920_ISADMA, dma);
writereg(dev, PP_SelfCTL, selfcontrol);
writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON);
writereg(dev, PP_LineCTL, lp->linectl & ~AUI_ONLY);
writereg(dev, PP_TestCTL,
writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK);
writereg(dev, PP_LineCTL, (lp->linectl & ~AUTO_AUI_10BASET) | AUI_ONLY);
writereg(dev, PP_LineCTL, (lp->linectl & ~AUTO_AUI_10BASET) | AUI_ONLY);
writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ);
writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON);
writereg(dev, PP_BusCTL, 0); /* disable interrupts. */
writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ);
writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON);
writereg(dev, PP_IA + i * 2,
writereg(dev, PP_BusCTL, MEMORY_ON);
writereg(dev, PP_LineCTL,
writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ);
writereg(dev, PP_CS8900_ISAINT, 0);
writereg(dev, PP_CS8920_ISAINT, 0);
writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8));
writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON);
writereg(dev, PP_RxCTL, DEF_RX_ACCEPT);
writereg(dev, PP_RxCFG, lp->curr_rx_cfg);
writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL |
writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL |
writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ);
writereg(dev, PP_TxCMD, lp->send_cmd);
writereg(dev, PP_TxLength, skb->len);
writereg(dev, PP_RxCFG, 0);
writereg(dev, PP_TxCFG, 0);
writereg(dev, PP_BufCFG, 0);
writereg(dev, PP_BusCTL, 0);
writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode);
writereg(dev, PP_RxCFG, lp->curr_rx_cfg |
writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8));
writereg(par, DTG_CONTROL, ctrlreg);
writereg(par, PLL_C, tmp);
writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
writereg(par, PLL_POSTDIV, tmp | 0x9);
writereg(par, PLL_POSTDIV, tmp);
writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
writereg(par, DTG_HORIZ_EXTENT, htot - 1);
writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
writereg(par, DTG_HSYNC_END,
writereg(par, DTG_HSYNC_END_COMP,
writereg(par, DTG_VERT_EXTENT,
writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
writereg(par, DTG_VSYNC_END,
writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
writereg(par, DTG_CONTROL, ctrlreg);
writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
writereg(par, DFA_FB_A, dfa_ctl);
writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
writereg(par, WAT_CTRL + (i << 4), 0);
writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
writereg(par, SYNC_CTL, ctrlreg);
writereg(par, CMAP + reg * 4, cmap_entry);
writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
writereg(par, SYNC_CTL, ctrl);
writereg(par, DISP_CTL, dctl);