arch/arm64/kvm/hyp/vgic-v3-sr.c

100

write_gicreg(val, ICH_LR11_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

1029

write_gicreg(vmcr, ICH_VMCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

103

write_gicreg(val, ICH_LR12_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

106

write_gicreg(val, ICH_LR13_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

1069

write_gicreg(vmcr, ICH_VMCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

109

write_gicreg(val, ICH_LR14_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

112

write_gicreg(val, ICH_LR15_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

121

write_gicreg(val, ICH_AP0R0_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

124

write_gicreg(val, ICH_AP0R1_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

127

write_gicreg(val, ICH_AP0R2_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

130

write_gicreg(val, ICH_AP0R3_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

139

write_gicreg(val, ICH_AP1R0_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

142

write_gicreg(val, ICH_AP1R1_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

145

write_gicreg(val, ICH_AP1R2_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

148

write_gicreg(val, ICH_AP1R3_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

246

write_gicreg(0, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

261

write_gicreg(compute_ich_hcr(cpu_if), ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

298

write_gicreg(ICC_SRE_EL1_SRE, ICC_SRE_EL1);

arch/arm64/kvm/hyp/vgic-v3-sr.c

301

write_gicreg(0, ICC_SRE_EL1);

arch/arm64/kvm/hyp/vgic-v3-sr.c

303

write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

325

write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,

arch/arm64/kvm/hyp/vgic-v3-sr.c

337

write_gicreg(vgic_ich_hcr_trap_bits() | ICH_HCR_EL2_En, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

347

write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

352

write_gicreg(1, ICC_SRE_EL1);

arch/arm64/kvm/hyp/vgic-v3-sr.c

362

write_gicreg(0, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

485

write_gicreg(0, ICC_SRE_EL1);

arch/arm64/kvm/hyp/vgic-v3-sr.c

490

write_gicreg(sre, ICC_SRE_EL1);

arch/arm64/kvm/hyp/vgic-v3-sr.c

523

write_gicreg(vmcr, ICH_VMCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

67

write_gicreg(val, ICH_LR0_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

70

write_gicreg(val, ICH_LR1_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

73

write_gicreg(val, ICH_LR2_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

76

write_gicreg(val, ICH_LR3_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

79

write_gicreg(val, ICH_LR4_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

799

write_gicreg(hcr, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

82

write_gicreg(val, ICH_LR5_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

85

write_gicreg(val, ICH_LR6_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

88

write_gicreg(val, ICH_LR7_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

91

write_gicreg(val, ICH_LR8_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

94

write_gicreg(val, ICH_LR9_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

97

write_gicreg(val, ICH_LR10_EL2);

drivers/irqchip/irq-gic-v3.c

1167

write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);

drivers/irqchip/irq-gic-v3.c

1201

write_gicreg(0, ICC_AP0R3_EL1);

drivers/irqchip/irq-gic-v3.c

1202

write_gicreg(0, ICC_AP0R2_EL1);

drivers/irqchip/irq-gic-v3.c

1205

write_gicreg(0, ICC_AP0R1_EL1);

drivers/irqchip/irq-gic-v3.c

1209

write_gicreg(0, ICC_AP0R0_EL1);

drivers/irqchip/irq-gic-v3.c

1218

write_gicreg(0, ICC_AP1R3_EL1);

drivers/irqchip/irq-gic-v3.c

1219

write_gicreg(0, ICC_AP1R2_EL1);

drivers/irqchip/irq-gic-v3.c

1222

write_gicreg(0, ICC_AP1R1_EL1);

drivers/irqchip/irq-gic-v3.c

1226

write_gicreg(0, ICC_AP1R0_EL1);

drivers/irqchip/irq-gic-v3.c

672

write_gicreg(irqd_to_hwirq(d), ICC_EOIR1_EL1);

drivers/irqchip/irq-gic-v3.c

773

write_gicreg(irqnr, ICC_EOIR1_EL1);

drivers/irqchip/irq-gic-v3.c

800

write_gicreg(irqnr, ICC_EOIR1_EL1);