Symbol: write_csr
drivers/firewire/core-card.c
756
.write_csr = dummy_write_csr,
drivers/firewire/core-transaction.c
1322
card->driver->write_csr(card, reg, be32_to_cpu(*data));
drivers/firewire/core-transaction.c
1329
card->driver->write_csr(card, CSR_STATE_CLEAR,
drivers/firewire/core.h
100
void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
drivers/firewire/ohci.c
3519
.write_csr = ohci_write_csr,
drivers/infiniband/hw/hfi1/chip.c
10140
write_csr(dd, SEND_LEN_CHECK0, len1);
drivers/infiniband/hw/hfi1/chip.c
10141
write_csr(dd, SEND_LEN_CHECK1, len2);
drivers/infiniband/hw/hfi1/chip.c
10167
write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
drivers/infiniband/hw/hfi1/chip.c
10190
write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
drivers/infiniband/hw/hfi1/chip.c
10369
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
drivers/infiniband/hw/hfi1/chip.c
10370
write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
drivers/infiniband/hw/hfi1/chip.c
10373
write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
drivers/infiniband/hw/hfi1/chip.c
10374
write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
drivers/infiniband/hw/hfi1/chip.c
10375
write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
drivers/infiniband/hw/hfi1/chip.c
10376
write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
drivers/infiniband/hw/hfi1/chip.c
10378
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
drivers/infiniband/hw/hfi1/chip.c
10381
write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
drivers/infiniband/hw/hfi1/chip.c
10382
write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
drivers/infiniband/hw/hfi1/chip.c
10389
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
drivers/infiniband/hw/hfi1/chip.c
10390
write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
drivers/infiniband/hw/hfi1/chip.c
10391
write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
drivers/infiniband/hw/hfi1/chip.c
10466
write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
drivers/infiniband/hw/hfi1/chip.c
10822
write_csr(dd, DCC_CFG_LED_CNTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
10986
write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
drivers/infiniband/hw/hfi1/chip.c
11158
write_csr(dd, target + (i * 8), reg);
drivers/infiniband/hw/hfi1/chip.c
11254
write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
drivers/infiniband/hw/hfi1/chip.c
11272
write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
drivers/infiniband/hw/hfi1/chip.c
11308
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
11319
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
11336
write_csr(dd, addr, reg);
drivers/infiniband/hw/hfi1/chip.c
11353
write_csr(dd, addr, reg);
drivers/infiniband/hw/hfi1/chip.c
12076
write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
drivers/infiniband/hw/hfi1/chip.c
12079
write_csr(dd, RCV_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
13178
write_csr(dd, CCE_INT_MASK + (8 * idx), reg);
drivers/infiniband/hw/hfi1/chip.c
13225
write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13227
write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13228
write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13229
write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13230
write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13231
write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13232
write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13233
write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13239
write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13240
write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13241
write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
drivers/infiniband/hw/hfi1/chip.c
13269
write_csr(dd, CCE_INT_MAP + (8 * m), reg);
drivers/infiniband/hw/hfi1/chip.c
13300
write_csr(dd, CCE_INT_MAP + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13523
write_csr(dd, RCV_PARTITION_KEY +
drivers/infiniband/hw/hfi1/chip.c
13547
write_csr(dd, CCE_INT_MAP + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13576
write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
1358
write_csr(dd, csr, value);
drivers/infiniband/hw/hfi1/chip.c
13594
write_csr(dd, CCE_CTRL, ctrl_bits);
drivers/infiniband/hw/hfi1/chip.c
13625
write_csr(dd, CCE_SCRATCH + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13627
write_csr(dd, CCE_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13628
write_csr(dd, CCE_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13631
write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13632
write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
drivers/infiniband/hw/hfi1/chip.c
13635
write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13636
write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
drivers/infiniband/hw/hfi1/chip.c
13641
write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13642
write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13645
write_csr(dd, CCE_INT_MAP, 0);
drivers/infiniband/hw/hfi1/chip.c
13648
write_csr(dd, CCE_INT_MASK + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13649
write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13654
write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13663
write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13664
write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13665
write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13672
write_csr(dd, MISC_CFG_RSA_CMD, 1);
drivers/infiniband/hw/hfi1/chip.c
13673
write_csr(dd, MISC_CFG_RSA_MU, 0);
drivers/infiniband/hw/hfi1/chip.c
13674
write_csr(dd, MISC_CFG_FW_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13680
write_csr(dd, MISC_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13681
write_csr(dd, MISC_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13693
write_csr(dd, SEND_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13699
write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
drivers/infiniband/hw/hfi1/chip.c
13702
write_csr(dd, SEND_PIO_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13703
write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13706
write_csr(dd, SEND_DMA_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13707
write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13710
write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13711
write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13713
write_csr(dd, SEND_BTH_QP, 0);
drivers/infiniband/hw/hfi1/chip.c
13714
write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
drivers/infiniband/hw/hfi1/chip.c
13715
write_csr(dd, SEND_SC2VLT0, 0);
drivers/infiniband/hw/hfi1/chip.c
13716
write_csr(dd, SEND_SC2VLT1, 0);
drivers/infiniband/hw/hfi1/chip.c
13717
write_csr(dd, SEND_SC2VLT2, 0);
drivers/infiniband/hw/hfi1/chip.c
13718
write_csr(dd, SEND_SC2VLT3, 0);
drivers/infiniband/hw/hfi1/chip.c
13719
write_csr(dd, SEND_LEN_CHECK0, 0);
drivers/infiniband/hw/hfi1/chip.c
13720
write_csr(dd, SEND_LEN_CHECK1, 0);
drivers/infiniband/hw/hfi1/chip.c
13722
write_csr(dd, SEND_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13723
write_csr(dd, SEND_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13726
write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13728
write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13730
write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13732
write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13734
write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13735
write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
drivers/infiniband/hw/hfi1/chip.c
13736
write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
drivers/infiniband/hw/hfi1/chip.c
13738
write_csr(dd, SEND_CM_TIMER_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13739
write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
drivers/infiniband/hw/hfi1/chip.c
13740
write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
drivers/infiniband/hw/hfi1/chip.c
13741
write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
drivers/infiniband/hw/hfi1/chip.c
13742
write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
drivers/infiniband/hw/hfi1/chip.c
13744
write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13745
write_csr(dd, SEND_CM_CREDIT_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
13750
write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13838
write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
drivers/infiniband/hw/hfi1/chip.c
13875
write_csr(dd, RCV_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
13881
write_csr(dd, RCV_BTH_QP, 0);
drivers/infiniband/hw/hfi1/chip.c
13882
write_csr(dd, RCV_MULTICAST, 0);
drivers/infiniband/hw/hfi1/chip.c
13883
write_csr(dd, RCV_BYPASS, 0);
drivers/infiniband/hw/hfi1/chip.c
13884
write_csr(dd, RCV_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
13886
write_csr(dd, RCV_ERR_INFO,
drivers/infiniband/hw/hfi1/chip.c
13889
write_csr(dd, RCV_ERR_MASK, 0);
drivers/infiniband/hw/hfi1/chip.c
13890
write_csr(dd, RCV_ERR_CLEAR, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
13893
write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13895
write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13897
write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13899
write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13903
write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
13953
write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13959
write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13965
write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13971
write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13979
write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
13983
write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
drivers/infiniband/hw/hfi1/chip.c
14023
write_csr(dd, SEND_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14029
write_csr(dd, RCV_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14031
write_csr(dd, RCV_CTXT_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14034
write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
drivers/infiniband/hw/hfi1/chip.c
14042
write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
drivers/infiniband/hw/hfi1/chip.c
14082
write_csr(dd, CCE_DC_CTRL, 0);
drivers/infiniband/hw/hfi1/chip.c
14097
write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
drivers/infiniband/hw/hfi1/chip.c
14098
write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
drivers/infiniband/hw/hfi1/chip.c
14131
write_csr(dd, SEND_BTH_QP,
drivers/infiniband/hw/hfi1/chip.c
14135
write_csr(dd, RCV_BTH_QP,
drivers/infiniband/hw/hfi1/chip.c
14185
write_csr(dd, regno, reg);
drivers/infiniband/hw/hfi1/chip.c
14245
write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
drivers/infiniband/hw/hfi1/chip.c
14264
write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
drivers/infiniband/hw/hfi1/chip.c
14268
write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
drivers/infiniband/hw/hfi1/chip.c
14275
write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
drivers/infiniband/hw/hfi1/chip.c
14287
write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
drivers/infiniband/hw/hfi1/chip.c
14288
write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
drivers/infiniband/hw/hfi1/chip.c
14289
write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
drivers/infiniband/hw/hfi1/chip.c
14540
write_csr(dd, regoff, reg);
drivers/infiniband/hw/hfi1/chip.c
14634
write_csr(dd, RCV_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14665
write_csr(dd, RCV_BYPASS, val);
drivers/infiniband/hw/hfi1/chip.c
14672
write_csr(dd, CCE_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14674
write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
drivers/infiniband/hw/hfi1/chip.c
14676
write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14677
write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14691
write_csr(dd, csr0to3,
drivers/infiniband/hw/hfi1/chip.c
14698
write_csr(dd, csr4to7,
drivers/infiniband/hw/hfi1/chip.c
14726
write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14727
write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14728
write_csr(dd, SEND_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14729
write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
drivers/infiniband/hw/hfi1/chip.c
14745
write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
drivers/infiniband/hw/hfi1/chip.c
14947
write_csr(dd, CCE_INT_MASK, 0ull);
drivers/infiniband/hw/hfi1/chip.c
14953
write_csr(dd, CCE_INT_CLEAR, all_bits);
drivers/infiniband/hw/hfi1/chip.c
14959
write_csr(dd, CCE_INT_FORCE, all_bits);
drivers/infiniband/hw/hfi1/chip.c
14965
write_csr(dd, CCE_INT_CLEAR, all_bits);
drivers/infiniband/hw/hfi1/chip.c
14966
write_csr(dd, CCE_INT_MASK, mask);
drivers/infiniband/hw/hfi1/chip.c
14970
write_csr(dd, CCE_INT_MASK, mask);
drivers/infiniband/hw/hfi1/chip.c
15397
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
drivers/infiniband/hw/hfi1/chip.c
15440
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
drivers/infiniband/hw/hfi1/chip.c
5684
write_csr(dd, SEND_EGRESS_ERR_INFO, info);
drivers/infiniband/hw/hfi1/chip.c
6100
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
drivers/infiniband/hw/hfi1/chip.c
6136
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
drivers/infiniband/hw/hfi1/chip.c
6191
write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
drivers/infiniband/hw/hfi1/chip.c
6202
write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
drivers/infiniband/hw/hfi1/chip.c
6326
write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
drivers/infiniband/hw/hfi1/chip.c
6348
write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
drivers/infiniband/hw/hfi1/chip.c
6369
write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET);
drivers/infiniband/hw/hfi1/chip.c
6375
write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
drivers/infiniband/hw/hfi1/chip.c
6403
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
6424
write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
drivers/infiniband/hw/hfi1/chip.c
6426
write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
drivers/infiniband/hw/hfi1/chip.c
6440
write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
drivers/infiniband/hw/hfi1/chip.c
6441
write_csr(dd, SEND_CM_CREDIT_VL15, 0);
drivers/infiniband/hw/hfi1/chip.c
6442
write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
drivers/infiniband/hw/hfi1/chip.c
6481
write_csr(dd, DC_LCB_CFG_RUN, 0);
drivers/infiniband/hw/hfi1/chip.c
6483
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
drivers/infiniband/hw/hfi1/chip.c
6488
write_csr(dd, DCC_CFG_RESET, reg |
drivers/infiniband/hw/hfi1/chip.c
6493
write_csr(dd, DCC_CFG_RESET, reg);
drivers/infiniband/hw/hfi1/chip.c
6494
write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
drivers/infiniband/hw/hfi1/chip.c
6523
write_csr(dd, DC_DC8051_CFG_RST, 0x1);
drivers/infiniband/hw/hfi1/chip.c
6547
write_csr(dd, DC_DC8051_CFG_RST, 0ull);
drivers/infiniband/hw/hfi1/chip.c
6554
write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
drivers/infiniband/hw/hfi1/chip.c
6556
write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
drivers/infiniband/hw/hfi1/chip.c
6634
write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
drivers/infiniband/hw/hfi1/chip.c
6645
write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
drivers/infiniband/hw/hfi1/chip.c
6647
write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
drivers/infiniband/hw/hfi1/chip.c
6649
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
drivers/infiniband/hw/hfi1/chip.c
6722
write_csr(dd, RCV_CTRL, rcvctrl);
drivers/infiniband/hw/hfi1/chip.c
6747
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
6896
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
6900
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
6902
write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
drivers/infiniband/hw/hfi1/chip.c
7500
write_csr(dd, DC_LCB_CFG_CRC_MODE,
drivers/infiniband/hw/hfi1/chip.c
7506
write_csr(dd, SEND_CM_CTRL,
drivers/infiniband/hw/hfi1/chip.c
7509
write_csr(dd, SEND_CM_CTRL,
drivers/infiniband/hw/hfi1/chip.c
7570
write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
drivers/infiniband/hw/hfi1/chip.c
7574
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
drivers/infiniband/hw/hfi1/chip.c
7577
write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
drivers/infiniband/hw/hfi1/chip.c
7845
write_csr(dd, DC_DC8051_ERR_EN,
drivers/infiniband/hw/hfi1/chip.c
8308
write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
drivers/infiniband/hw/hfi1/chip.c
8341
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
8364
write_csr(dd, addr, rcd->imask);
drivers/infiniband/hw/hfi1/chip.c
8372
write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
drivers/infiniband/hw/hfi1/chip.c
8565
write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
drivers/infiniband/hw/hfi1/chip.c
8673
write_csr(dd, addr, data);
drivers/infiniband/hw/hfi1/chip.c
8703
write_csr(dd, addr, data);
drivers/infiniband/hw/hfi1/chip.c
8776
write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
drivers/infiniband/hw/hfi1/chip.c
8787
write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
drivers/infiniband/hw/hfi1/chip.c
8789
write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
drivers/infiniband/hw/hfi1/chip.c
8826
write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
drivers/infiniband/hw/hfi1/chip.c
9200
write_csr(dd, DC_LCB_CFG_LOOPBACK,
drivers/infiniband/hw/hfi1/chip.c
9202
write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
drivers/infiniband/hw/hfi1/chip.c
9207
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
drivers/infiniband/hw/hfi1/chip.c
9212
write_csr(dd, DC_LCB_CFG_RUN,
drivers/infiniband/hw/hfi1/chip.c
9219
write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
drivers/infiniband/hw/hfi1/chip.c
9237
write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
drivers/infiniband/hw/hfi1/chip.c
9252
write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
drivers/infiniband/hw/hfi1/chip.c
9270
write_csr(dd, DC_DC8051_CFG_MODE,
drivers/infiniband/hw/hfi1/chip.c
9512
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
drivers/infiniband/hw/hfi1/chip.c
9518
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
drivers/infiniband/hw/hfi1/chip.c
9535
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
9541
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
9729
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
drivers/infiniband/hw/hfi1/chip.c
9731
write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
drivers/infiniband/hw/hfi1/chip.c
9739
write_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
9762
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
drivers/infiniband/hw/hfi1/chip.c
9763
write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
drivers/infiniband/hw/hfi1/chip.c
9764
write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
drivers/infiniband/hw/hfi1/chip.c
9765
write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
drivers/infiniband/hw/hfi1/chip.c
9766
write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
drivers/infiniband/hw/hfi1/chip.c
9767
write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
drivers/infiniband/hw/hfi1/chip.c
9768
write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
drivers/infiniband/hw/hfi1/chip.h
576
void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
drivers/infiniband/hw/hfi1/chip.h
594
write_csr(dd, offset0 + (0x100 * ctxt), value);
drivers/infiniband/hw/hfi1/chip.h
629
write_csr(dd, offset0 + (0x1000 * ctxt), value);
drivers/infiniband/hw/hfi1/debugfs.c
1012
write_csr(dd, ASIC_GPIO_OUT, gpio_val);
drivers/infiniband/hw/hfi1/debugfs.c
1013
write_csr(dd, ASIC_GPIO_OE, gpio_val);
drivers/infiniband/hw/hfi1/debugfs.c
551
write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
drivers/infiniband/hw/hfi1/driver.c
1313
write_csr(dd, DCC_CFG_LED_CNTRL, 0);
drivers/infiniband/hw/hfi1/eprom.c
152
write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
drivers/infiniband/hw/hfi1/eprom.c
154
write_csr(dd, ASIC_EEP_CTL_STAT,
drivers/infiniband/hw/hfi1/eprom.c
158
write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
drivers/infiniband/hw/hfi1/eprom.c
51
write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset));
drivers/infiniband/hw/hfi1/eprom.c
54
write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */
drivers/infiniband/hw/hfi1/firmware.c
1000
write_csr(dd, DC_DC8051_CFG_RST, 0ull);
drivers/infiniband/hw/hfi1/firmware.c
1036
write_csr(dd, ASIC_CFG_SBUS_REQUEST,
drivers/infiniband/hw/hfi1/firmware.c
1100
write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
drivers/infiniband/hw/hfi1/firmware.c
1110
write_csr(dd, MISC_CFG_FW_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
1180
write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
drivers/infiniband/hw/hfi1/firmware.c
1203
write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
drivers/infiniband/hw/hfi1/firmware.c
1369
write_csr(dd, ASIC_CFG_MUTEX, mask);
drivers/infiniband/hw/hfi1/firmware.c
1385
write_csr(dd, ASIC_CFG_MUTEX, 0);
drivers/infiniband/hw/hfi1/firmware.c
1403
write_csr(dd, ASIC_CFG_MUTEX, 0);
drivers/infiniband/hw/hfi1/firmware.c
1462
write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit);
drivers/infiniband/hw/hfi1/firmware.c
1524
write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
drivers/infiniband/hw/hfi1/firmware.c
1578
write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
drivers/infiniband/hw/hfi1/firmware.c
1602
write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
drivers/infiniband/hw/hfi1/firmware.c
1618
write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
drivers/infiniband/hw/hfi1/firmware.c
2165
write_csr(dd, CCE_DC_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
237
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
drivers/infiniband/hw/hfi1/firmware.c
239
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
drivers/infiniband/hw/hfi1/firmware.c
274
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
drivers/infiniband/hw/hfi1/firmware.c
283
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
306
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
drivers/infiniband/hw/hfi1/firmware.c
311
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
drivers/infiniband/hw/hfi1/firmware.c
325
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
drivers/infiniband/hw/hfi1/firmware.c
342
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
343
write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
drivers/infiniband/hw/hfi1/firmware.c
745
write_csr(dd, what + (8 * i), *ptr);
drivers/infiniband/hw/hfi1/firmware.c
752
write_csr(dd, what + (8 * i), value);
drivers/infiniband/hw/hfi1/firmware.c
768
write_csr(dd, what, *ptr);
drivers/infiniband/hw/hfi1/firmware.c
787
write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
drivers/infiniband/hw/hfi1/firmware.c
803
write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
drivers/infiniband/hw/hfi1/firmware.c
868
write_csr(dd, MISC_ERR_CLEAR,
drivers/infiniband/hw/hfi1/firmware.c
958
write_csr(dd, DC_DC8051_CFG_RST, reg);
drivers/infiniband/hw/hfi1/firmware.c
970
write_csr(dd, DC_DC8051_CFG_RST, reg);
drivers/infiniband/hw/hfi1/firmware.c
978
write_csr(dd, MISC_CFG_FW_CTRL, 0);
drivers/infiniband/hw/hfi1/firmware.c
992
write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
drivers/infiniband/hw/hfi1/hfi.h
2369
write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
drivers/infiniband/hw/hfi1/hfi.h
2371
write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
drivers/infiniband/hw/hfi1/init.c
532
write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
drivers/infiniband/hw/hfi1/mad.c
1762
write_csr(dd, SEND_SC2VLT0, *val++);
drivers/infiniband/hw/hfi1/mad.c
1763
write_csr(dd, SEND_SC2VLT1, *val++);
drivers/infiniband/hw/hfi1/mad.c
1764
write_csr(dd, SEND_SC2VLT2, *val++);
drivers/infiniband/hw/hfi1/mad.c
1765
write_csr(dd, SEND_SC2VLT3, *val++);
drivers/infiniband/hw/hfi1/mad.c
3631
write_csr(dd, RCV_ERR_INFO,
drivers/infiniband/hw/hfi1/pcie.c
1022
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
drivers/infiniband/hw/hfi1/pcie.c
1234
write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
drivers/infiniband/hw/hfi1/pcie.c
1289
write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
drivers/infiniband/hw/hfi1/pcie.c
1311
write_csr(dd, CCE_DC_CTRL, 0);
drivers/infiniband/hw/hfi1/pcie.c
1367
write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
drivers/infiniband/hw/hfi1/pcie.c
831
write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
drivers/infiniband/hw/hfi1/pcie.c
850
write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
drivers/infiniband/hw/hfi1/pcie.c
925
write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
drivers/infiniband/hw/hfi1/pio.c
1225
write_csr(dd, SEND_PIO_ERR_CLEAR,
drivers/infiniband/hw/hfi1/pio.c
1230
write_csr(dd, SEND_PIO_INIT_CTXT,
drivers/infiniband/hw/hfi1/pio.c
1303
write_csr(dd, SEND_PIO_INIT_CTXT, pio);
drivers/infiniband/hw/hfi1/pio.c
23
write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
drivers/infiniband/hw/hfi1/pio.c
81
write_csr(dd, SEND_CTRL, reg);
drivers/infiniband/hw/hfi1/qsfp.c
43
write_csr(dd, target_oe, reg);
drivers/infiniband/hw/hfi1/qsfp.c
67
write_csr(dd, target_oe, reg);
drivers/infiniband/hw/hfi1/sdma.c
3361
write_csr(sde->dd,
drivers/net/ethernet/amd/pcnet32.c
1006
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
drivers/net/ethernet/amd/pcnet32.c
1057
lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
drivers/net/ethernet/amd/pcnet32.c
1060
lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
drivers/net/ethernet/amd/pcnet32.c
1079
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
drivers/net/ethernet/amd/pcnet32.c
1115
a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
drivers/net/ethernet/amd/pcnet32.c
1406
lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
drivers/net/ethernet/amd/pcnet32.c
1415
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
1418
lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
drivers/net/ethernet/amd/pcnet32.c
1719
a->write_csr(ioaddr, 80,
drivers/net/ethernet/amd/pcnet32.c
1920
a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
drivers/net/ethernet/amd/pcnet32.c
1921
a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
drivers/net/ethernet/amd/pcnet32.c
1936
a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
drivers/net/ethernet/amd/pcnet32.c
2153
lp->a->write_csr(ioaddr, 124, val);
drivers/net/ethernet/amd/pcnet32.c
2257
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
2273
lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
drivers/net/ethernet/amd/pcnet32.c
2274
lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
drivers/net/ethernet/amd/pcnet32.c
2276
lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
drivers/net/ethernet/amd/pcnet32.c
2277
lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
drivers/net/ethernet/amd/pcnet32.c
2295
lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
drivers/net/ethernet/amd/pcnet32.c
243
void (*write_csr) (unsigned long, int, u16);
drivers/net/ethernet/amd/pcnet32.c
2444
lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
drivers/net/ethernet/amd/pcnet32.c
2450
lp->a->write_csr(ioaddr, CSR0, csr0_bits);
drivers/net/ethernet/amd/pcnet32.c
2463
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
2542
lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
drivers/net/ethernet/amd/pcnet32.c
2573
lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
drivers/net/ethernet/amd/pcnet32.c
2606
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
2643
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
2693
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2694
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2695
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2696
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
drivers/net/ethernet/amd/pcnet32.c
2710
lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
drivers/net/ethernet/amd/pcnet32.c
2732
lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
drivers/net/ethernet/amd/pcnet32.c
2736
lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
drivers/net/ethernet/amd/pcnet32.c
2743
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
383
.write_csr = pcnet32_wio_write_csr,
drivers/net/ethernet/amd/pcnet32.c
438
.write_csr = pcnet32_dwio_write_csr,
drivers/net/ethernet/amd/pcnet32.c
464
lp->a->write_csr(ioaddr, CSR3, val);
drivers/net/ethernet/amd/pcnet32.c
690
a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
drivers/net/ethernet/amd/pcnet32.c
715
lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
drivers/net/ethernet/amd/pcnet32.c
763
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
drivers/net/ethernet/amd/pcnet32.c
776
lp->a->write_csr(ioaddr, CSR15, csr15);
drivers/net/ethernet/amd/pcnet32.c
894
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
drivers/net/ethernet/amd/pcnet32.c
992
lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
drivers/net/ethernet/amd/pcnet32.c
998
lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */