arch/arc/include/asm/irqflags-arcv2.h

134

write_aux_reg(AUX_IRQ_HINT, irq);

arch/arc/include/asm/irqflags-arcv2.h

139

write_aux_reg(AUX_IRQ_HINT, 0);

arch/arc/include/asm/irqflags-arcv2.h

83

write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff);

arch/arc/include/asm/mmu-arcv2.h

84

write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);

arch/arc/include/asm/mmu-arcv2.h

91

write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);

arch/arc/kernel/fpu.c

63

write_aux_reg(ARC_REG_FPU_CTRL, 0x100);

arch/arc/kernel/fpu.c

66

write_aux_reg(ARC_REG_FPU_STATUS, fwe);

arch/arc/kernel/fpu.c

78

write_aux_reg(ARC_REG_FPU_CTRL, restore->ctrl);

arch/arc/kernel/fpu.c

79

write_aux_reg(ARC_REG_FPU_STATUS, (fwe | restore->status));

arch/arc/kernel/intc-arcv2.c

101

write_aux_reg(AUX_IRQ_SELECT, data->hwirq);

arch/arc/kernel/intc-arcv2.c

102

write_aux_reg(AUX_IRQ_ENABLE, 0);

arch/arc/kernel/intc-arcv2.c

107

write_aux_reg(AUX_IRQ_SELECT, data->hwirq);

arch/arc/kernel/intc-arcv2.c

108

write_aux_reg(AUX_IRQ_ENABLE, 1);

arch/arc/kernel/intc-arcv2.c

114

write_aux_reg(AUX_IRQ_SELECT, data->hwirq);

arch/arc/kernel/intc-arcv2.c

115

write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);

arch/arc/kernel/intc-arcv2.c

122

write_aux_reg(AUX_IRQ_ENABLE, 1);

arch/arc/kernel/intc-arcv2.c

80

write_aux_reg(AUX_IRQ_SELECT, i);

arch/arc/kernel/intc-arcv2.c

81

write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);

arch/arc/kernel/intc-arcv2.c

89

write_aux_reg(AUX_IRQ_ENABLE, 0);

arch/arc/kernel/intc-compact.c

35

write_aux_reg(AUX_IRQ_LEV, level_mask);

arch/arc/kernel/intc-compact.c

49

write_aux_reg(AUX_IENABLE, ienb);

arch/arc/kernel/intc-compact.c

70

write_aux_reg(AUX_IENABLE, ienb);

arch/arc/kernel/intc-compact.c

79

write_aux_reg(AUX_IENABLE, ienb);

arch/arc/kernel/perf_event.c

271

write_aux_reg(ARC_REG_PCT_INDEX, idx);

arch/arc/kernel/perf_event.c

273

write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);

arch/arc/kernel/perf_event.c

394

write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);

arch/arc/kernel/perf_event.c

402

write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);

arch/arc/kernel/perf_event.c

435

write_aux_reg(ARC_REG_PCT_INDEX, idx);

arch/arc/kernel/perf_event.c

438

write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));

arch/arc/kernel/perf_event.c

439

write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));

arch/arc/kernel/perf_event.c

468

write_aux_reg(ARC_REG_PCT_INT_CTRL,

arch/arc/kernel/perf_event.c

472

write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */

arch/arc/kernel/perf_event.c

473

write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */

arch/arc/kernel/perf_event.c

487

write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));

arch/arc/kernel/perf_event.c

488

write_aux_reg(ARC_REG_PCT_INT_CTRL,

arch/arc/kernel/perf_event.c

494

write_aux_reg(ARC_REG_PCT_INDEX, idx);

arch/arc/kernel/perf_event.c

497

write_aux_reg(ARC_REG_PCT_CONFIG, 0);

arch/arc/kernel/perf_event.c

535

write_aux_reg(ARC_REG_PCT_INDEX, idx);

arch/arc/kernel/perf_event.c

541

write_aux_reg(ARC_REG_PCT_INT_CNTL,

arch/arc/kernel/perf_event.c

543

write_aux_reg(ARC_REG_PCT_INT_CNTH,

arch/arc/kernel/perf_event.c

547

write_aux_reg(ARC_REG_PCT_CONFIG, 0);

arch/arc/kernel/perf_event.c

548

write_aux_reg(ARC_REG_PCT_COUNTL, 0);

arch/arc/kernel/perf_event.c

549

write_aux_reg(ARC_REG_PCT_COUNTH, 0);

arch/arc/kernel/perf_event.c

585

write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));

arch/arc/kernel/perf_event.c

592

write_aux_reg(ARC_REG_PCT_INT_CTRL,

arch/arc/kernel/perf_event.c

629

write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);

arch/arc/kernel/perf_event.c

776

write_aux_reg(ARC_REG_CC_INDEX, i);

arch/arc/mm/cache.c

1084

write_aux_reg(ARC_REG_IC_PTAG_HI, 0);

arch/arc/mm/cache.c

1087

write_aux_reg(ARC_REG_DC_PTAG_HI, 0);

arch/arc/mm/cache.c

1090

write_aux_reg(ARC_REG_SLC_RGN_END1, 0);

arch/arc/mm/cache.c

1091

write_aux_reg(ARC_REG_SLC_RGN_START1, 0);

arch/arc/mm/cache.c

220

write_aux_reg(aux_tag, paddr);

arch/arc/mm/cache.c

230

write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);

arch/arc/mm/cache.c

234

write_aux_reg(aux_tag, paddr);

arch/arc/mm/cache.c

238

write_aux_reg(aux_cmd, vaddr);

arch/arc/mm/cache.c

285

write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);

arch/arc/mm/cache.c

287

write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);

arch/arc/mm/cache.c

291

write_aux_reg(aux_cmd, paddr);

arch/arc/mm/cache.c

331

write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);

arch/arc/mm/cache.c

333

write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);

arch/arc/mm/cache.c

337

write_aux_reg(e, paddr + sz); /* ENDR is exclusive */

arch/arc/mm/cache.c

338

write_aux_reg(s, paddr);

arch/arc/mm/cache.c

371

write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);

arch/arc/mm/cache.c

395

write_aux_reg(ctl, val);

arch/arc/mm/cache.c

413

write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);

arch/arc/mm/cache.c

434

write_aux_reg(aux, 0x1);

arch/arc/mm/cache.c

444

write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);

arch/arc/mm/cache.c

451

write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);

arch/arc/mm/cache.c

491

write_aux_reg(ARC_REG_IC_IVIC, 1);

arch/arc/mm/cache.c

582

write_aux_reg(ARC_REG_SLC_CTRL, ctrl);

arch/arc/mm/cache.c

591

write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));

arch/arc/mm/cache.c

593

write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));

arch/arc/mm/cache.c

596

write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));

arch/arc/mm/cache.c

598

write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));

arch/arc/mm/cache.c

636

write_aux_reg(ARC_REG_SLC_CTRL, ctrl);

arch/arc/mm/cache.c

646

write_aux_reg(cmd, paddr);

arch/arc/mm/cache.c

672

write_aux_reg(r, ctrl);

arch/arc/mm/cache.c

675

write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);

arch/arc/mm/cache.c

677

write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);

arch/arc/mm/cache.c

691

write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);

arch/arc/mm/cache.c

698

write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);

arch/arc/mm/cache.c

972

write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);

arch/arc/mm/cache.c

980

write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);

arch/arc/mm/cache.c

981

write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);

arch/arc/mm/cache.c

982

write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);

arch/arc/mm/tlb.c

103

write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);

arch/arc/mm/tlb.c

110

write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);

arch/arc/mm/tlb.c

111

write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);

arch/arc/mm/tlb.c

116

write_aux_reg(ARC_REG_TLBPD0, pd0);

arch/arc/mm/tlb.c

119

write_aux_reg(ARC_REG_TLBPD1, pd1);

arch/arc/mm/tlb.c

121

write_aux_reg(ARC_REG_TLBPD1, pd1 & 0xFFFFFFFF);

arch/arc/mm/tlb.c

122

write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);

arch/arc/mm/tlb.c

125

write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);

arch/arc/mm/tlb.c

144

write_aux_reg(ARC_REG_TLBPD1, 0);

arch/arc/mm/tlb.c

147

write_aux_reg(ARC_REG_TLBPD1HI, 0);

arch/arc/mm/tlb.c

149

write_aux_reg(ARC_REG_TLBPD0, 0);

arch/arc/mm/tlb.c

153

write_aux_reg(ARC_REG_TLBINDEX, entry);

arch/arc/mm/tlb.c

154

write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);

arch/arc/mm/tlb.c

161

write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);

arch/arc/mm/tlb.c

164

write_aux_reg(ARC_REG_TLBINDEX, entry);

arch/arc/mm/tlb.c

165

write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);

arch/arc/mm/tlb.c

31

write_aux_reg(ARC_REG_TLBPD1, 0);

arch/arc/mm/tlb.c

34

write_aux_reg(ARC_REG_TLBPD1HI, 0);

arch/arc/mm/tlb.c

36

write_aux_reg(ARC_REG_TLBPD0, 0);

arch/arc/mm/tlb.c

37

write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);

arch/arc/mm/tlb.c

42

write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);

arch/arc/mm/tlb.c

51

write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);

arch/arc/mm/tlb.c

53

write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);

arch/arc/mm/tlb.c

664

write_aux_reg(ARC_REG_TLBPD1HI, 0);

arch/arc/mm/tlb.c

714

write_aux_reg(ARC_REG_TLBINDEX,

arch/arc/mm/tlb.c

716

write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);

arch/arc/mm/tlb.c

747

write_aux_reg(ARC_REG_TLBINDEX,

arch/arc/mm/tlb.c

93

write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);

arch/arc/mm/tlb.c

96

write_aux_reg(ARC_REG_TLBPD1, pd1);

drivers/clocksource/arc_timer.c

182

write_aux_reg(AUX_RTC_CTRL, 1);

drivers/clocksource/arc_timer.c

226

write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);

drivers/clocksource/arc_timer.c

227

write_aux_reg(ARC_REG_TIMER1_CNT, 0);

drivers/clocksource/arc_timer.c

228

write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH);

drivers/clocksource/arc_timer.c

245

write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);

drivers/clocksource/arc_timer.c

246

write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */

drivers/clocksource/arc_timer.c

248

write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH);

drivers/clocksource/arc_timer.c

297

write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH);

include/soc/arc/arc_aux.h

51

write_aux_reg(reg, tmp); \

include/soc/arc/mcip.h

119

write_aux_reg(ARC_REG_MCIP_WDATA, data);